OFC50: The Era of High-Speed Silicon Photonics Has Arrived! TSMC’s SiN Waveguide Powers NVIDIA’s Photonic Ambitions
Original Articles by SemiVision Research (OFC50)
SemiVision Research believes that the next phase of collaboration between NVIDIA and TSMC in silicon photonics technology will focus on optimizing edge couplers to achieve higher bandwidth optical engines. Specifically, improvements will be made in the coupling design between waveguides and optical fibers, involving precise adjustments to reverse taper structures, careful selection of dielectric layer materials, and substrate undercut techniques. These efforts will significantly reduce coupling losses and enhance optical signal stability. As single-channel bandwidth scales up from 200G to 400G and beyond, reducing insertion losses and polarization-dependent losses (PDL) at the edge coupler becomes crucial. This progress will enable integration of more wavelengths and higher-density optical channels within the same optical engine, thereby expanding the overall performance and competitiveness of optoelectronic integration modules for data centers, AI computing, and HPC applications.
In recent years, TSMC has published numerous research papers and patents aimed at strengthening silicon photonics integration. According to TSMC’s technology forums, the ultimate goal of silicon photonics is to achieve chip-to-chip (C2C) interconnections. However, this represents a significant challenge, demanding substantial investment in time, space, and highly integrated packaging solutions. TSMC’s frequent publications on advanced silicon photonics techniques demonstrate its proactive strategy for future development. Silicon photonics must leverage the advantages of optical signals but also rely on efficient electrical signal transmission, highlighting the importance of serializer-deserializer (SerDes) technology. Additionally, for high-frequency transmission, signal amplification is essential, thus necessitating close attention to transimpedance amplifiers (TIA), such as those utilizing SiGe BiCMOS processes.
Research Background and Motivation
Silicon photonics (SiPh), characterized by its high bandwidth, energy efficiency, and scalability, has increasingly attracted interest from data centers, high-performance computing (HPC), artificial intelligence (AI), and 5G/6G communication sectors. Leveraging mature CMOS fabrication processes, SiPh platforms exhibit not only superior performance but also cost advantages associated with large-scale production.
Currently, TSMC primarily utilizes a 65nm CMOS process for SiPh device fabrication. However, modulators predominantly based on microring structures present significant lithography challenges for foundries, due to strict requirements on lithography windows, process tolerance, critical dimension (CD) control, and etch control.
To fulfill future bandwidth demands of data centers, photonic integrated circuits (PICs) must incorporate:
Capability for multiple wavelength channel transmission • High optical power handling (~21 dBm), to support an increased number of waveguide splits, evolving from the current mainstream 1:4 split to 1:8 or even higher (such as 1:16), imposing greater challenges on fabrication technology. • Advancement from current 200G/lane to 400G/lane transmission rates, accompanied by necessary upgrades in SerDes technology from existing 224G to 448G. Presently, only Broadcom demonstrates capability in 448G SerDes technology, while Marvell and MediaTek (MTK) remain primarily at 224G, necessitating continued monitoring of Broadcom's developments to achieve 400G/lane implementation.
Moreover, future PIC platforms must effectively support advanced technologies like wavelength division multiplexing (WDM) and pulse amplitude modulation (PAM4), crucial for overcoming traditional optical communication challenges such as bandwidth bottlenecks, signal density limitations, and excessive power consumption. In a previous article, SemiVision Research discussed why Nvidia and Broadcom chose different design approaches for CPO switches. For more details, please refer to the link below.
Conventional pure silicon (Si) devices suffer significant optical losses at high power due to two-photon absorption (TPA) and free-carrier absorption (FCA), alongside high thermal sensitivity attributed to their elevated thermo-optic coefficient (~1.8×10⁻⁴ /K).
In contrast, silicon nitride (SiN) demonstrates a lower thermo-optic coefficient (~2.5×10⁻⁵ /K) and reduced nonlinear losses, effectively handling high optical power, thus positioning SiN as an ideal complementary material for SiPh platforms. Nonetheless, achieving high-performance, uniform SiN devices on a 300mm wafer manufacturing platform remains technically challenging.
Therefore, this research aims to integrate high-quality SiN thin films, produced through advanced plasma-enhanced chemical vapor deposition (PECVD), into existing silicon photonic platforms, systematically validating photonic component performance, process uniformity, and reliability.
For Paid Members , SemiVision Research will discuss following topics:
The Rise of Photonic AI: TSMC’s SiN Technology Empowers NVIDIA’s Optical Ambitions
Improvement of SiN Photonic Component Performance
SiN Waveguide Bend Design
Improvement of SiN-to-Si Waveguide Transition Components
Optimization of SiN Edge Coupler (EC)
Research Conclusion
TSMC SoIC-X COUPE Roadmap and plaining to Optical I/O for Feynman
Global Silicon Photonic Ecosystem
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