2025 VLSI-Beyond Scaling: BSPDN Process Innovation through CMP and ALD in the Angstrom Era
Original Articles By SemiVision Research (Samsung , TSMC, Intel ,Nvidia , AMAT , ASM , LAM , TEL , SPTS ,EVG ,EBARA)
From Process-Driven to System-Driven: The Path Forward for CMOS Technology in the Ångström Era
As CMOS technology enters the Ångström era, the traditional advantages of dimensional scaling are rapidly diminishing. In his keynote at VLSI 2025, Samsung’s Vice President Keunhwi Cho presented a clear trajectory: the future of CMOS will not be defined solely by smaller nodes, but by multi-level, system-driven innovations across materials, architecture, packaging, and integration.
1. Backside Power Delivery (BSPDN): Overcoming Power Integrity Bottlenecks
With increasing power densities and the rise of 3D stacked architectures, conventional front-side power delivery networks (FSPDN) face serious limitations in IR drop and signal interference. Backside Power Delivery offers a transformative solution. By routing power through backside vias (TSVs, BCs, or VBPR structures), BSPDN minimizes resistance and inductance, improves power efficiency, and decouples power and signal paths. Companies like TSMC and Samsung are co-optimizing BSPDN alongside GAA to enhance voltage stability in ultra-dense AI SoCs.
2. Heterogeneous Integration: Toward Modular, Functionally Specialized Systems
Heterogeneous integration is becoming the cornerstone of post-Moore innovation. Instead of a monolithic SoC, system architects are embracing chiplets, logic-memory fusion, and sensor integration—each fabricated on the most suitable node. Samsung’s roadmap includes GAA-based logic co-packaged with MRAM, image sensors, and HBM through 2.5D and 3D packaging, enabling modular SoC platforms with high bandwidth, low latency, and domain-specific performance tuning.
3. 3D IC: Redefining Density and Performance Amid Thermal and Signal Challenges
3D IC stacking unlocks unprecedented compute density and interconnect proximity. However, it also introduces complex thermal management and signal integrity challenges. Cho emphasizes that advances in lithography alone are no longer sufficient. Next-generation EDA tools must support multi-physics co-simulation—integrating thermal modeling, power network analysis, and die-to-die signal timing—to ensure reliable and scalable 3D systems.
4. Silicon Photonics: Enabling Next-Gen Interconnects in the Data-Driven Era
As AI models scale into trillions of parameters, the need for high-bandwidth, low-power interconnects becomes urgent. Traditional copper-based links struggle to meet performance demands across chiplets and memory domains. Silicon Photonics (SiPh) emerges as a foundational technology, offering high-speed optical links with energy efficiency and spatial scalability. Samsung, along with other industry leaders, is investing in SiPh platforms and co-packaged optics (CPO) to embed photonics into logic-memory architectures and data center systems.
Beyond Scaling—The Era of System-Level Co-Optimization
The Ångström era demands more than transistor miniaturization. From backside power delivery and heterogeneous chiplet design to 3D stacking and photonic interconnects, the future of CMOS will be defined by system-level co-optimization. As Cho noted, the real breakthroughs will come not from narrower gate lengths alone, but from cross-domain collaboration—spanning devices, interconnects, packaging, and architecture. This is how CMOS will continue to evolve beyond Moore’s Law.
For Paid Members ,SemiVision will discuss topics on
Backside Power Delivery: A Key Technology to Solve Metal Congestion and Power Efficiency Challenges
Process Flow of Backside Power Rail (BSPDN)
CMP and ALD: Synergistic Roles in BSPDN
Performance Gains and Technical Challenges in BSPDN
Backside Power Delivery Network (BSPDN): A Strategic Enabler in the Ångström Era of Advanced Semiconductor Manufacturing
1.Samsung: Co-Development of GAA and BSPDN
2.TSMC: Super Power Rail (SPR) as the Industry Benchmark
3.Intel: Commercializing PowerVia Ahead of the Industry
4.NVIDIA: AI SoC Power Demands Drive BSPDN Adoption
5.Applied Materials (AMAT): Backside Process Equipment Leader
6.ASM International: ALD Pioneer for BSPDN Needs
7.LAM Research: TSV and Backside Etch Specialist
8.Tokyo Electron (TEL): Etch and Surface Engineering Innovator
9.SPTS (a KLA Company): TSV & Backside Etch Specialist
10.EV Group (EVG): Enabling Wafer Bonding & Ultra-Thin Processing
11.EBARA’s Role and Value in BSPDN Backside Processing
The Era of Heterogeneous Integration: Chiplet Architectures and the Trillion-Transistor Leap
From N5 to A10: Process Shrink and Packaging Innovation in Tandem
Advanced Packaging and 3D IC: TSV and Hybrid Bonding Usher in a New Era of Heterogeneous Integration
Hybrid Bonding: A Breakthrough for Interconnect Density
3D IC: From Packaging Stacking to a Core Enabler of Performance and Power Efficiency
Silicon Photonics: Redefining Interconnect Architecture for Data Centers
Co-Packaged Optics (CPO): The Future of Silicon Photonics and Switch Chip Integration
Key Elements in TSMC’s Heterogeneous Integration Platform
System-Level Management: Evolving from Functional Verification to Multidimensional Integration and Collaboration
System-Level Thermal Management: Overcoming Thermal Bottlenecks in 3D IC and BSPDN Designs
From Power Delivery to Thermo-Mechanical Co-Design — A New Era for 3D IC Thermal Management
