2025 VLSI Tech Forum : TSMC Announces the lastest concept of SiPh from Circuit design's viewpoint
Original Articles By SemiVision Research (IEEE VLSI , TSMC ）
2025 VLSI Symposium Concludes Successfully: A Five-Day Immersive Journey into Semiconductor Design
The 2025 VLSI Technology and Circuits Symposium recently came to a successful close. This five-day global conference was truly a marathon of knowledge—bringing together top experts from leading companies and research institutions to share cutting-edge developments in chip design, process technologies, and system-level integration. It stood out as a highly professional and content-dense technical forum.
One of the major highlights of the event was the Short Course program, which served as an intensive, condensed version of a graduate-level training series. For anyone looking to deepen their understanding of semiconductor design and logic-process co-integration, this was an invaluable learning opportunity. The curriculum covered a wide range of topics, from fundamental circuit design and device physics to advanced logic and process integration strategies—requiring a solid technical foundation to fully grasp the insights shared.
With VLSI now concluded, the next major event on the calendar is the 2025 Device Research Conference (DRC)—a key symposium for those focused on breakthrough device technologies and materials.
As the 2025 VLSI Symposium draws to a close, the global spotlight in the semiconductor community now shifts to another premier event—the 2025 Device Research Conference (DRC). Following in the footsteps of VLSI, DRC brings together leading experts from academia and industry to delve into the latest advances in electronic and photonic devices. These two back-to-back conferences together capture the full spectrum of semiconductor innovation—from system architecture to device physics—highlighting the industry’s continued momentum and groundbreaking research in the era of AI.
Introduction to the 2025 Symposium on VLSI Technology & Circuits
The 45th Symposium on VLSI Technology & Circuits is set to take place from June 8–12, 2025 at the Rihga Royal Hotel in Kyoto, Japan . Centered on the theme “Cultivating the VLSI Garden: From Seeds of Innovation to Thriving Growth”, this premier international event will bring together leading experts across the full spectrum of VLSI—from materials and device innovation to circuit design, packaging, system architecture, and cutting-edge applications .
Over the course of five days, attendees can expect:
In-depth technical sessions: Plenary talks, evening panels, and joint focus symposia.
Hands-on learning: Workshops and short courses led by industry and academic experts.
Engaging demos: A live showcase of around 15–20 selected papers, enabling direct interaction with authors .
Celebration of emerging talent: Best Student Paper and Best Demo Paper awards highlighting outstanding contributions .
This weeklong event will explore breakthroughs in AI acceleration, 3D packaging, photonic interconnects, multi-core and edge computing, IoT and biomedical integration, VR/AR, robotics, autonomous systems, and beyond .
Media Collaboration – BtB Integrated Marketing
BtB Integrated Marketing, represented by Chris Burke (Co-Media Relations Director), will act as the official media partner for North America and Europe . With over 30 years of experience, BtB specializes in B2B communications—offering strategic support in public relations, media planning, event exhibition, and digital content. Their involvement guarantees robust media exposure and amplifies the Symposium’s impact across global tech communities .
With its rich blend of scholarly rigor, industry relevance, technical depth, and media amplification, the 2025 VLSI Symposium promises a dynamic forum for shaping the future of semiconductor innovation—and you’re invited to be part of it!
If you missed the 2025 Symposium on VLSI Technology & Circuits, be sure to keep an eye on the upcoming Device Research Conference (DRC). As one of the most respected international conferences in the field of semiconductor and nanoscale device innovation, DRC offers deep academic insight and cutting-edge research on next-generation transistors, memory technologies, sensors, quantum devices, and advanced materials.
Complementing the system-level and integration focus of VLSI, DRC provides a critical platform for exploring the frontiers of device physics and breakthrough architectures. This year’s conference is expected to feature high-impact papers from leading universities and research institutions worldwide. For researchers, technologists, and industry leaders aiming to stay at the forefront of device innovation, DRC is not to be missed.
Stay tuned to the official conference website for updates on program highlights, paper deadlines, and registration details.
It is worth noting that the major international conferences in the semiconductor and electronic components industry—including ECTC (Electronic Components and Technology Conference), VLSI Symposium, DRC (Device Research Conference), and the year-end flagship IEDM (International Electron Devices Meeting)—are all co-organized or supported by BtB Marketing Communications.
BtB plays a key role in driving the marketing communications, event coordination, and promotional strategy for these highly respected technical forums. Their long-standing involvement demonstrates their professional standing and global influence in the high-tech industry. BtB also provides exhibitors and speakers with strategic brand positioning, content support, and efficient communications outreach across media and audience channels.
SemiVision’s Curated Highlights from VLSI 2025: Key Technologies You Must Know
To help readers grasp the most essential takeaways from this year’s VLSI Symposium, SemiVision has curated a set of in-depth feature analyses focused on the core technologies shaping the semiconductor industry’s next wave. These highlights center on topics that sit at the crossroads of market relevance and technical inflection.
TSMC’s Dual Focus: CMOS Scaling and Silicon Photonics Design Strategy
At this year’s Short Course, TSMC led two high-profile panel discussions, each addressing a pivotal dimension of future semiconductor design:
Continued CMOS Scaling in Advanced Nodes
Methodologies and Integration Strategies in Silicon Photonics
Among the two, the silicon photonics panel attracted significant attention. TSMC not only explored the co-design challenges of Photonic Integrated Circuits (PICs) and Electronic Integrated Circuits (EICs), but also introduced its development flow based on the integrated Photonics Design Kit (iPDK). This approach represents a more structured and modular design framework for PIC development, moving silicon photonics design toward systematization and broader ecosystem compatibility.
Key Technical Focus: 3D Optical Interconnect Design for Silicon Photonics
In SemiVision’s upcoming coverage, we will delve into what we believe is one of the most critical and instructive topics from the Short Course: 3D Optical Interconnect Design.
This session not only explained the fundamentals of PIC architecture, but also unpacked the architectural evolution of optical interconnects, packaging-level integration strategies, and emerging methodologies such as co-design and co-optimization. Furthermore, it provided insight into the future deployment of optical interconnects in AI and HPC system architectures.
For readers seeking to understand the trajectory of the silicon photonics industry, the rise of 3D integration, and the technical challenges associated with stacking photonic and electronic domains, this will serve as a well-rounded entry point into both foundational and advanced perspectives.
For Paid Members, SemiVision will discuss topics on
The Core Bottlenecks of AI Chips: Memory Walls and Interconnect Limits Are Driving a Deep Communication Gap
AI Chips Are Getting Stronger—But Bandwidth Scaling Is Even More Critical
Bandwidth Scaling Is the Next Frontier (Optical Chiplet)
Bandwidth Scaling with Optical Interconnects: A Three-Pronged Strategy—Wavelength, Modulation, and Symbol Rate
Optical I/O Breakthroughs Require Simultaneous Advancement Across All Three Dimensions
TSMC HPC Technology Platform: Strategic Deployment of Opto-Electronic Integration for Next-Generation Bandwidth
COUPE + SerDes Coupling: Defining a New Bandwidth Floor
Switch Market Landscape: Broadcom vs. Marvell vs. Nvidia
The Real Bandwidth Race Lies in the Depth of Integration: Packaging, SerDes, and Optical Engines
TSMC COUPE: A Fully Integrated 3D Photonic-Electronic Engine
3D Stacking: More Than Moore Complexity Requires More Than Moore Know-how
Optical I/O: From Fiber to PIC with Sub-micron Precision
Electrical Die (N7)– Explanation of Terms
Photonic Die (SOI 65nm) – Explanation of Terms
Optical I/O – Explanation of Terms
3D Stacking – Explanation of Terms
Overview of Optical Transmit and Receive in WDM-Based Interconnect Systems
Key Photonic Material Properties in Optical Communication: Loss, Bandgap, and Wavelength Compatibility