2025 VLSI Technology Forum : Challenges and Opportunity of compact modeling in the AI Era
Original Article by SemiVision Research (TSMC , Nvidia , Broadcom , Marvell , GUC ,AiChip )
The 2025 IEEE VLSI-TSA, organized by the Industrial Technology Research Institute (ITRI), will be held from April 21 to 24, 2025, at the Ambassador Hotel Hsinchu.
This premier annual event will bring together more than 60 leading experts from across industry, academia, and research institutions to provide comprehensive insights into semiconductor technology trends and emerging market opportunities.
Join us to engage with key figures shaping the future of the semiconductor industry.
SemiVision also participated in this conference and gained valuable insights into the latest developments in the semiconductor industry.
In this article, we aim to share key takeaways from the session, particularly focusing on simulation methodologies and SPICE models, which are essential concepts for all semiconductor designers.
The session, led by TSMC, covered the fundamental knowledge required by design teams at companies like NVIDIA, Google, MediaTek, Marvell, and Broadcom before Tape-Out, emphasizing the importance of understanding the physical and silicon-based electronic properties of the target technology node.
We will also introduce several key device physics concepts, such as device corners, SPICE models, and more—critical knowledge for any engineer entering the semiconductor industry.
Compact Model: Definition, Value, and Industry Evolution
1. What is a Compact Model and Why It Matters
The Essence of Modeling in Semiconductor Engineering
A model is not merely a set of mathematical equations. It is a systematic abstraction of complex physical behaviors, transforming real-world physics into a form that engineering tools can compute efficiently. From Newton’s Laws to Maxwell’s Equations, Schrödinger’s Equation, and the foundations of semiconductor device physics, all are generalized forms of modeling.
A Compact Model is a practical engineering abstraction derived from these theories, specifically optimized for high-speed, high-accuracy circuit simulation. It translates advanced physics into SPICE-compatible mathematical expressions, enabling designers to simulate device behaviors like MOSFETs, BJTs, FinFETs, and GAAFETs across various design scales.
Value Proposition
Without Compact Models, validating designs using TCAD simulations or silicon characterization would be prohibitively expensive, slow, and inefficient. Compact Models reduce simulation costs by several orders of magnitude, enabling multi-condition, multi-level, and multi-physics verification, from device-level to system-level.
Application Scope
Device-Level: Modeling MOSFETs, BJTs, Diodes, and passive elements.
Circuit-Level: Simulating amplifiers, PLLs, oscillators, etc.
System-Level: Power, performance, and reliability analysis of SoCs.
Process Development: Modeling process variations and reliability.
Multi-Physics Simulation: Electro-thermal, opto-electronic, and mechanical-electrical coupling.
The Role of Standardization
Standardized models such as BSIM (Berkeley Short-channel IGFET Model) have become industry benchmarks, enabling ecosystem-wide compatibility between EDA tools and foundries. As process nodes advance to 3nm, 2nm, and beyond, Compact Models must capture more advanced physical effects such as quantum tunneling and short-channel phenomena, further elevating their critical role in the semiconductor industry.
SPICE’s Central Role in the EDA Ecosystem and Its Cross-Domain Expansion
SPICE as the Simulation Backbone
SPICE (Simulation Program with Integrated Circuit Emphasis) serves as the computational core of EDA workflows, supporting everything from basic electrical circuits to advanced Compact Models like BSIM, HiSIM, and PSP. Its differential equation-based solver framework, typically leveraging Newton-Raphson methods, extends beyond electrical simulation to multi-physics domains.
Cross-Domain Applications
Electro-Thermal Coupling: Simulates thermal effects on power devices (e.g., IGBTs).
Photonic Simulation: Models phase modulation and optical losses in silicon photonics.
Mechanical Simulation: Simulates MEMS mechanical behavior using equivalent circuits.
Bio-Chemical Sensor Simulation: Models impedance characteristics of biosensors.
Toolchain Integration
Modern design flows integrate 2.5D/3D RC extraction, 3D capacitance models, TCAD-to-SPICE behavioral mapping, and system-level simulations, as seen in tools like Synopsys Custom Compiler and Cadence Virtuoso, providing end-to-end design verification.
How AI is Revolutionizing Compact Model Development
Traditional Parameter Extraction Challenges
Heavy reliance on manual tuning and expert knowledge.
Susceptibility to local minima, leading to non-optimal solutions.
Long development cycles and low robustness when handling process variability.
AI-Enhanced Parameter Extraction with Bayesian Optimization
Machine learning algorithms autonomously explore high-dimensional parameter spaces.
Balances global exploration and local precision, reducing manual effort.
Accelerates model fitting while improving accuracy and efficiency.
Neural Network-Based Modeling (NN-Platform) — Breaking Analytical Limits
Overcomes the limitations of manually derived closed-form equations.
Learns high-dimensional, non-linear device behaviors including thermal effects and variability.
Proven by research from UC Berkeley (UCB) and IIT, demonstrating superior model consistency and efficiency, especially for FinFETs and emerging devices.
Industrial Adoption Potential
Rapidly adapts to new device architectures like 2D material transistors and memristors.
Addresses industry challenges related to interpretability and computational overhead.
The Future with Large Language Models (LLMs) and Workflow Automation
The increasing complexity of tools, models, and data has made cross-team communication and knowledge management a productivity bottleneck.
LLM-Driven Design Process Automation
AI Assistants/Agents to parse documentation, suggest parameters, diagnose errors, and optimize workflows.
System-to-System automation to bridge gaps between tools and teams, reducing manual communication costs.
Enabling seamless collaboration between process development, model development, design teams, and EDA vendors, boosting overall productivity and time-to-market.
Real-World Examples
Early commercial solutions like Synopsys DSO.ai are already using AI for design space exploration.
Future LLM integration could automate netlist generation, design rule checking (DRC), and even parameter tuning, transforming EDA workflows from design intent to simulation.
Compact Models are the backbone of semiconductor design verification, bridging the gap between physics and engineering practicality. Their evolution, powered by AI-driven automation and next-generation modeling platforms, will continue to define the future of semiconductor innovation, unlocking new levels of accuracy, efficiency, and scalability in the design and manufacturing process.
After understanding these foundational concepts, we will now focus on TSMC’s perspective on the “Challenges and Opportunities of Compact Modeling in the AI Era.”
This discussion is essential for readers aiming to enter the fields of IC design or semiconductor manufacturing (foundry). Without this knowledge, it is difficult to fully grasp the front-end requirements of AI chip development, particularly in IP qualification and design verification.
Understanding how Compact Models support the transition from device physics to system-level simulation is critical for ensuring design accuracy, manufacturability, and performance validation—key steps before Tape-Out in any advanced AI chip development flow.
