From Glass Fiber to CCL: The Material Backbone Powering the New Era of CoWoP Packaging
Original Articles By SemiVision Research ( Nvidia ,TSMC ,TUC, EMC, Unimicron, Resonac, MGC, Panasonic , Nan Ya PCB)
In the modern high-performance electronics and semiconductor packaging industry, every step of the material structure and supply chain directly determines product performance, reliability, and mass-production capability. At the most fundamental level, glass fiber combined with low dielectric constant and low-loss epoxy or PPO resin (Low Dk/Df Epoxy/PPO), laminated with copper foil, forms CCL (Copper Clad Laminate). CCL is a core material for the electronics industry, providing the essential base layer for high-frequency and high-speed circuits, and is dominated by suppliers such as TUC, EMC, Unimicron, Resonac, MGC, and Panasonic.
In advanced packaging processes, CCL serves as the core layer, which is then built up with ABF (Ajinomoto Build-up Film) and fine-pitch processing to create advanced package substrates. These substrates act as the critical bridge between chip modules and the system, enabling signal fan-out, power distribution, and mechanical support. They are indispensable for modern high-performance processors, GPUs, and AI accelerators.
However, as chip sizes grow, HBM stack layers increase, and signal rates push toward 112G / 224G SerDes, package substrates face severe challenges in warpage and thermo-mechanical mismatch in large-area, multi-layer designs. This is especially critical in ultra-large packaging solutions like CoWoS (Chip-on-Wafer-on-Substrate), where the thermal expansion and structural stability of the substrate become key limiting factors for yield and manufacturability.
From materials to packaging structure—glass fiber, resin, copper foil, CCL, ABF, and finally the substrate—every layer forms the foundation for high-performance computing and AI systems. How to continually control warpage and signal/power loss in this era of high speed, high frequency, and high power consumption is the central challenge driving future innovation in advanced packaging and material engineering.
One of the hottest topics in Taiwan’s technology and semiconductor industry recently is the appearance of CoWoP (Chip-on-Wafer-on-PCB) in NVIDIA’s latest technology roadmap. The industry already has a deep understanding of CoWoS (Chip-on-Wafer-on-Substrate), which is the primary packaging technology for top-tier AI accelerators such as the H100 and H200. As CoPoS (Chip-on-Panel-on-Substrate) panel-level packaging concepts begin to take shape, the next step is to further simplify the packaging hierarchy by replacing the “on Substrate” portion of CoWoS with a direct connection to the PCB, which has led to the emergence of the bold CoWoP concept.
The essence of CoWoP is to eliminate the traditional ABF package substrate and allow the chip and silicon interposer module to mount directly onto a high-precision PCB (typically an SLP, or Substrate-Like PCB), creating a direct link from the chip level to the system board. This design theoretically brings several advantages:
Shorter signal paths and lower insertion loss, which are critical for high-speed interconnects such as NVLink, PCIe Gen6/7, and HBM3/4.
Greater flexibility in thermal and mechanical design, as the bare die is directly exposed on the PCB, making it easier to implement direct-contact cold plates or liquid cooling—highly beneficial for kilowatt-class AI GPUs.
However, from a technical feasibility perspective, CoWoP presents far greater challenges than current CoWoS or CoPoS approaches, including:
PCB precision requirements: The system board must take over the high-density routing role of the original package substrate, achieving line width/spacing of 15–20 μm or less, while maintaining strict flatness and dimensional stability.
Thermo-mechanical reliability: With bare dies and interposers directly mounted on the PCB, thermal cycling and CTE (coefficient of thermal expansion) mismatch can cause solder fatigue and amplified warpage risks.
Manufacturing and yield challenges: Traditional PCB factories would need to upgrade to near-advanced-packaging cleanroom and process standards (ISO Class 1–5), and post-assembly yields must be virtually defect-free.
According to discussions with Taiwanese PCB and packaging manufacturers, proof-of-concept samples have indeed been submitted for testing, indicating that NVIDIA’s CoWoP approach is not just theoretical but is undergoing early-stage technical validation. However, the industry consensus is that CoWoP will not be used for mass production in the NVIDIA Rubin Ultra generation, and NVIDIA is more likely to continue with a mix of CoWoS and CoPoS solutions to ensure product reliability and supply stability.
CoWoP represents a potential future direction for system-level packaging, but due to challenges in manufacturing precision, cleanroom requirements, and yield control, the Rubin Ultra generation will still primarily rely on CoWoS. True commercialization of CoWoP may require at least one to two more product generations before it can reshape the packaging models and supply chain ecosystem for HPC and AI servers.
It can therefore be concluded that the core concept of CoWoP is to replace the traditional CoWoS structure, where the silicon interposer rests on a package substrate and PCB, with a single ultra-thin SLP (Substrate-Like PCB)that serves both functions.
For Paid Members ,SemiVision will discuss topics on
Origin and Technical Analysis of CoWoP
PCB Manufacturing Methods and SLP/MSAP
mSAP and Optical Modules as Early Catalysts
HVLP (High-Frequency Very Low Profile) Copper Foil and Ultra-Thin Copper Foil Market Analysis
Shin‑Etsu Chemical Develops Innovative Equipment and Methods for Advanced Packaging Substrates
AI Accelerators Driving Demand for CCL and PCB
What is Glass Fabric?
Electronic-Grade Glass Fiber Fabric for Special Composite Materials
Glass fiber manufacturing
Electronic fabric is a key reinforcement material for copper-clad laminates (CCL).
Key Technical Parameters of Electronic Fabric: Dielectric Constant & Dielectric Loss
Why Does Signal Transmission Through Copper Get Affected by the Dielectric Constant / Dielectric Loss of Electronic Fabric?
Impact of Electronic Fabric on Copper Clad Laminate (CCL) Parameters
Specialty Electronic Glass Fabrics: Essential for AI Hardware, Devices, and Chip Packaging
224G High-Speed Interconnect Solutions Enter Research Stage
Development Highlights of Second-Generation Ultra-Low Df Quartz Electronic Fabric
