From Wafers to the World: VLSI Symposium Opens a New Chapter
Original Articles by SemiVision Research (2025 VLSI Symposium)
VLSI Symposium 2025 – Cultivating the Future of Innovation
Under the theme “Cultivating the VLSI Garden: From Seeds of Innovation to Thriving Growth,” the 2025 Symposium on VLSI Technology and Circuits brings the global semiconductor community together in Kyoto to explore the roots and future branches of our industry’s most transformative technologies.
As we enter a post-Moore era defined by the convergence of AI, heterogeneous integration, advanced memory, and system-level innovation, this year’s Symposium serves as a fertile ground for new ideas to take root. From process breakthroughs and 2D materials to edge intelligence and chiplet architectures, every session cultivates insights that will drive the next wave of semiconductor growth.
What distinguishes VLSI Symposium 2025 is its unique blend of industry-driven content and collaborative learning. With world-class contributions from IBM, AMD, TSMC, SK hynix, NVIDIA, MediaTek, Samsung, Sony, Lam Research, KIOXIA, and many more, the Symposium goes beyond technical exchange—it becomes a living garden of innovation where theory meets application, and seeds of research mature into real-world impact.
In this pivotal moment for our field, we gather not only to learn, but to co-create the ecosystem that will sustain the intelligent infrastructure of tomorrow. From the lab to the fab, and from circuits to systems, VLSI Symposium 2025 is where growth begins.
2025 Symposium on VLSI Technology and Circuits
About the Symposium
Professors Shoji Tanaka and Walter Kosonocky, founders of the Symposium, first organized the VLSI Technology Symposium in 1981 with the hope of offering an opportunity for world's top technologists to engage in an open exchange of ideas on what was quickly becoming a revolution in the world's industrial capability. Since then, the Symposium has been held annually and has grown to be an important and valuable event for people working in the VLSI business. The presentation of high-quality papers has made it possible for attendees to learn about new directions in the development of VLSI technology. The friendly atmosphere has made this an enjoyable learning experience.
The Symposium on VLSI Technology has alternated each year between sites in US and Japan. In 1987, the first Symposium on VLSI Circuits was held in conjunction with the Technology Symposium in recognition of the growing interest to provide the same small but intense and open forum for discussing circuit and system implementations. Since then, this annual meeting has increased its value over the past 30 years. We are confident that so many new technologies and circuits were introduced in the past Symposia and thus have contributed to the prosperity of the world. Its sponsors continue to be the IEEE Electron Devices Society and Solid-State Circuits Society, and the Japan Society of Applied Physics in cooperation with the Institute of Electronics, Information and Communication Engineers.
For many reasons, these meetings have remained linked for the past years to provide opportunities for technology people and circuit and system designers to interact with each other. These interactions are augmented with short courses, invited speakers and several evening panel discussions, Forums, Workshops. In recognition of the efforts of organizers, authors and participants to make the Symposia successful, there is ample banquet and entertainment prearranged.
In its 42nd year of delivering a unique convergence of technology and circuits for the microelectronics industry, the 2022 Symposium on VLSI Technology & Circuits had been merged into one Symposium to maximize the synergy across both domains.
【VLSI Symposium 2025 | Plenary Sessions Preview】
The VLSI Symposium 2025, taking place from June 9 to 13 in Kyoto, continues its tradition as the premier global gathering for semiconductor and circuit design professionals. This year’s two Plenary Sessions will spotlight the evolving landscape of Generative AI, Edge Intelligence, memory innovation, and the future of VLSI in the post-Moore era, offering rare insights from top industry leaders and innovators.
Plenary Session 1
Date & Time: Tuesday, June 10, 2025 – 8:00 A.M. to 10:00 A.M.
PL1-1｜Dr. Seon Yong Cha (CTO & Head of R&D, SK hynix)
Topic: Driving Innovation in DRAM Technology – Towards a Sustainable Future
Summary:
Dr. Cha, who has led several pivotal DRAM generations at SK hynix, will examine the challenges faced as memory technology reaches sub-10nm nodes. His talk will highlight how platform-based architectural design and innovation are key to meeting the demanding requirements of the AI era—especially in terms of bandwidth, latency, and scalability.
PL1-2｜Dr. John Y. Chen (Corporate VP of Technology & Foundry Management, NVIDIA)
PL1-2｜Dr. John Y. Chen (Corporate VP of Technology & Foundry Management, NVIDIA)
Topic: Innovate VLSI for AI Growth
Summary:
As AI development continues to surge, innovation in VLSI remains foundational. Dr. Chen will reflect on his leadership roles at TSMC, WaferTech, and NVIDIA, analyzing the innovation process from materials and process to modules and systems. Emphasizing the role of system-level thinking and talent development, he will discuss how VLSI innovation can overcome the post-Moore slowdown and enable the next wave of AI hardware evolution.
Plenary Session 2
Date & Time: Wednesday, June 11, 2025 – 8:00 A.M. to 10:00 A.M.
PL2-1｜Dr. Kou-Hung Lawrence Loh (Corporate SVP, MediaTek Inc. & President, MediaTek USA)
Topic: Enabling Generative AI: Innovations and Challenges in Semiconductor Design Technologies
Summary:
With the explosive growth of generative AI, chip architecture and design methodologies are being redefined. Dr. Loh will explore the required advancements across data center and edge computing platforms, including heterogeneous integration, power management, and design efficiency. He will share how MediaTek is leveraging SoC innovation to meet complex engineering challenges and shape the future AI infrastructure.
PL2-2｜Mr. Alessandro Cremonesi（EVP & Chief Innovation Officer, STMicroelectronics）
Topic: The Evolution of Edge AI: Contextual Awareness and Generative Intelligence
Summary:
As generative AI transitions from the cloud to the edge, sensing and compute capabilities must evolve in parallel. Mr. Cremonesi will detail how Edge AI can integrate sensing, NPUs, neuromorphic computing, and in-memory technologies to enable intelligent systems with contextual awareness. STMicroelectronics’ strategy emphasizes energy efficiency and real-time interaction, offering a vision of seamless, intelligent edge systems.
These two Plenary Sessions provide an exceptional opportunity to understand how VLSI technology is enabling next-generation AI infrastructure. From DRAM and SoC innovations to system-level design and Edge AI, VLSI Symposium 2025 is unveiling the roadmap for the future of semiconductor design.
VLSI Symposium 2025｜Industry-Led Technical Forums Officially Launched
Amid the sweeping transformation of semiconductor technology driven by AI and high-performance computing, VLSI Symposium 2025 kicks off on June 9 with two major technical forums: “Circuits and Systems for AI and Computing” and “Key VLSI Technologies in the AI Era.” These sessions cover the most cutting-edge topics—from AI hardware architecture, EDA, and chiplet design to advanced process nodes, 2D materials, and heterogeneous integration.
What makes these sessions particularly noteworthy is that they are almost entirely led and taught by the world’s leading technology companies. Speakers and instructors include experts from IBM, AMD, TSMC, SK hynix, Synopsys, KIOXIA, Samsung, Sony, and Lam Research. The content is deeply practical, showcasing how the industry is thinking about and executing the future of AI-era semiconductor innovation.
Circuits and Systems for AI and Computing
Time: June 9, 8:25 A.M. – 5:25 P.M.
Key Topics:
IBM: Hardware accelerator design for efficient generative AI models
AMD: Architectural trends in AI hardware platforms
University of Michigan & Synopsys: Modular chiplet strategies and AI for EDA
TSMC: Focus on 3D optical interconnect technologies
SK hynix: HBM’s critical role in AI computing
KIOXIA & NYCU: Power and memory architectures for generative AI systems
This session emphasizes system architecture, EDA, connectivity, memory, and power—building a comprehensive blueprint for AI-era chip design and deployment.
Key VLSI Technologies in the AI Era
Time: June 9, 8:25 A.M. – 4:35 P.M.
Key Topics:
TSMC: CMOS scaling and system-level integration
Purdue University: Latest insights into 2D materials
imec: Roadmap for 2.5D/3D heterogeneous system partitioning
Lam Research: Process and material innovations for logic and memory
Micron & SK hynix: DRAM history and emerging memory challenges
Samsung: DTCO/STCO optimization from device to system
Sony: 3D heterogeneous integration for CMOS image sensors
This session focuses on the foundational elements of AI-era manufacturing technology—from materials science and advanced packaging to system-level heterogenous integration.
These forums reflect a broader shift in the industry: from academic-driven research to industry-led knowledge transfer and collaboration. As AI accelerates its impact across the tech stack, engineering know-how and direct experience from corporate R&D teams are becoming the central learning resources for the community.
Through these highly practical technical tutorials and trend analyses, VLSI Symposium is evolving from a platform of technology showcase to a knowledge-intensive, industry-grounded learning hub.