GTC 2026 Outlook: How NVIDIA Is Redefining AI Infrastructure with LPX, CPO, and Rubin
Original Article By SemiVision Research [Reading time: 20 mins]
Introduction: Growth Drivers of AI Factories, Inference, and Training
The rapid advancement of generative AI and large language models is forcing a fundamental redesign of data-center computing architectures. In 2024, NVIDIA introduced the Blackwell GB200 NVL72, enabling a single rack to house 72 GPUs and 36 Grace CPUs, interconnected via NVLink 6 and Quantum X800 InfiniBand / Spectrum X Ethernet to deliver 400 Gb/s scale-out networking. These innovations significantly reduced training costs and dramatically lowered the cost per million tokens for inference workloads.
However, as model parameter counts continue to grow explosively, a single architecture must now support ultra-large models—including Mixture of Experts (MoE), long-context inference, and real-time audio/video processing. In response, NVIDIA is expected to unveil further breakthroughs at GTC 2026: LPX inference racks, CPX and NVL144, Rubin Ultra NVL576 with orthogonal backplanes and CPO optical interconnects, as well as transformational changes in PCB materials, cooling, and assembly processes.
This article takes a technology-focused perspective to provide a detailed overview of these upcoming platforms, interpreting them in the context of the latest publicly available information.
LPX Inference Racks: From LPUs to RealScale Ultra-Low-Latency Inference
LPX (Also Known as LPU): Design Philosophy
LPX is a new rack architecture designed by NVIDIA specifically for inference workloads, with its core rooted in NVIDIA’s licensing and acquisition of Groq’s LPU (Language Processing Unit) technology. Groq’s architecture places large amounts of memory directly on-chip, eliminating the bandwidth bottlenecks that traditional GPUs face when relying on external HBM or DRAM.
Groq LPUs integrate hundreds of megabits of on-chip SRAM and exploit deterministic execution optimized for sequential inference to maximize data reuse. The compiler schedules all computation and data movement at compile time, eliminating runtime bandwidth contention and enabling extremely low-latency token generation.
LPX extends this architecture to much larger scale. Groq’s RealScale network uses a direct, switch-less topology: each LPU connects directly to others, forming a network similar to a dragonfly-plus design. Because each LPU operates in a plesiosynchronous regime—where clock oscillators exhibit small, predictable drift—the compiler can precompute packet timing for every data transfer. As a result, 576 LPUs can operate as if they shared a single memory space. This deterministic scheduling allows near-linear scaling across multiple LPUs, making the architecture well suited for Mixture-of-Experts models and large language models with long-range dependencies.
Scaling LPX from 64 to 256 LPUs: Performance and Infrastructure Requirements
Following a licensing agreement with Groq in December 2025, NVIDIA’s initial LPX racks are expected to integrate 64 LPUs, packaged as 32 RealScale ASIC tiles. Each LPU contains hundreds of megabytes of on-chip SRAM, and when combined with RealScale’s deterministic network, the rack can generate small batches of tokens at millisecond-level latency. Groq demonstrations have shown that 10,000 “thought tokens” can be produced in roughly two seconds.
Around GTC 2026, NVIDIA plans to introduce an enhanced LPX rack featuring 256 LPUs per rack, a fourfold increase over the first generation. Paired with new 52-layer M9 Q-glass PCBs and larger on-chip memory capacity, NVIDIA aims to position LPX as a complement to Rubin GPUs in inference scenarios—covering workloads ranging from long-context reasoning to real-time speech and video generation.
M9 PCBs and 52-Layer Routing
Supporting the dense integration of 256 LPUs requires premium PCB materials. According to high-frequency PCB industry sources, NVIDIA is evaluating M9-class copper-clad laminates (M9 CCL) for the mid-plane designs of both CPX (the inference variant of Rubin) and LPX.
M9 laminates use Q-glass (high-end quartz fiber) with a dielectric constant of approximately 3.0 and a dissipation factor of 0.0007, significantly outperforming the E-glass used in conventional M8 CCLs. This enables low insertion loss at 56G–112G PAM4 and even 448G SerDes frequencies. M9 can also be hybridized with materials such as PTFE (polytetrafluoroethylene) to achieve even lower dielectric constants in selected layers.
For LPX, the 52-layer M9 PCB not only carries power and high-speed signal routing, but also integrates mounting points for liquid-cooling cold plates and RealScale connectors, ensuring tight synchronization across LPUs. The PCB value per LPU card is estimated at roughly USD 200 (not discussed further here, as this analysis focuses on technology rather than pricing). This underscores the critical role of PCB and materials suppliers in the success of LPX.
Thermal Management and Cooling
The high density of LPUs makes thermal management a key consideration. While individual Groq LPUs have relatively modest power consumption, operating 256 LPUs simultaneously can still result in tens of kilowatts per rack. Consequently, LPX adopts liquid-cooled cold plates, similar to the micro-channel cold plate (MCCP) technology used in the NVL72 VR200 platform. MCCP and related cooling innovations will be discussed in greater detail in the subsequent section on VR200.
The Relationship Between LPX and the Rubin Platform: Completing the Inference Stack
NVIDIA is adopting a layered architecture in its data-center strategy:
Blackwell / Grace — high-throughput platforms that combine training and inference;
Vera Rubin / Grace Rubin — HBM4-based GPUs paired with Vera CPUs, optimized for long-sequence inference and high-bandwidth models;
LPX — ultra-low-latency inference built on Groq LPUs, particularly well suited for single-batch, low-batch inference and real-time control;
CPX — a GDDR7-based variant of the Rubin architecture, focused on long-context prefill computation.
The goal of LPX is not to replace GPUs, but to tier inference workloads. When model sizes are relatively small and ultra-low latency is required, LPUs leverage large on-chip SRAM for acceleration. When models demand long-range memory or large token storage, CPX and Rubin GPUs provide greater HBM4/HBM4e capacity and higher FLOPS.
The RealScale network can also be bridged with NVLink interconnects, allowing LPX systems to scale into GPU-based platforms and form hybrid AI factories. In future Mixture-of-Experts (MoE) deployments, LPUs may serve as the gating networks, while Rubin GPUs compute the experts themselves—a hybrid model that is likely to become increasingly common in inference scenarios.
Below we will share:
Vera Rubin VR200 NVL72: A New-Generation Training and Inference Platform
CPX and NVL144: Platforms for Long-Context Inference
NVL576: Rubin Ultra and the Inflection Point of Orthogonal Backplanes and CPO
Networking and Communications: NVLink, Spectrum X, and Quantum X
Outlook and Forward-Looking Perspectives
Vera Rubin VR200 NVL72: A New-Generation Training and Inference Platform
