IMPACT 2025 Conference Review: Enabling Energy-Efficient AI with Advanced Logic, 3D Packaging, and Photonics
Original Article By SemiVision (TSMC, IEEE, VLSI, TPCA, IMPACT)
IMPACT 2025 Conference Review: Enabling Energy-Efficient AI with Advanced Logic, 3D Packaging, and Photonics
Since its inception in 2006, the IMPACT Conference has been at the forefront of technological evolution, fostering innovation in the packaging, PCB, and semiconductor industries. Over the past two decades, IMPACT has not only witnessed but actively contributed to rapid advancements in 5G, AI, high-performance computing (HPC), edge computing, and sustainability. Each year, the conference has adapted to the latest trends, driving forward the conversation on emerging technologies and their industrial applications.
Now in its 20th year, IMPACT 2025 embraces the theme “Energy-Efficient AI: From Cloud to Edge,” reflecting the industry’s growing emphasis on high-performance, low-power solutions. As AI applications continue to expand—from data centers to edge devices—the need for advanced PCB, IC substrates, heterogeneous integration, and packaging technologies has become increasingly critical.
This milestone year marks not just a celebration of the past 20 years, but a bold step into the future, where IMPACT continues to lead, inspire, and drive innovation. Join us at IMPACT 2025 as we shape the next era of AI, semiconductor packaging, and PCB technology—powering a smarter, more sustainable world.
Dr. Frank J. C. Lee, Vice President at TSMC, delivers the plenary “Enabling Energy-Efficient AI with Semiconductor Innovations” at IMPACT 2025. In this comprehensive review, we examine the key insights from TSMC’s presentations at IMPACT 2025 – the 20th International Microsystems, Packaging, Assembly and Circuits Technology Conference held in Taipei in October 2025. The central theme of the event, “Energy-Efficient AI: From Cloud to the Edge,” underscores an urgent industry focus on reducing power consumption even as AI compute workloads grow exponentially.
The plenary talk by Dr. Frank J. C. Lee of TSMC highlighted how AI’s proliferation from hyperscale data centers to edge devices is driving an exponential rise in compute demand and power usage, making energy efficiency a critical bottleneck to further progress. TSMC’s strategy to confront this challenge spans multiple technology domains: advanced silicon logic scaling (from FinFET to nanosheet transistors), 3D packaging and heterogeneous integration techniques, silicon photonics for optical I/O, and new energy-efficient design methodologies. By integrating innovations across process nodes, packaging, and system-level architecture, TSMC aims to dramatically improve performance-per-watt for AI chips and sustain the pace of AI advancements.
In summary, TSMC’s presentations at IMPACT 2025 demonstrated a holistic approach to enabling sustainable AI growth. Key announcements included the upcoming 2 nm (N2) semiconductor node with nanosheet transistors slated for volume production in 2025, which continues historical power-performance scaling (delivering ~30% power reduction each generation). Beyond transistor scaling, TSMC detailed breakthroughs in 3D Fabric packaging (chip stacking and chiplet integration), achieving multi-fold energy efficiency gains at the system level. The company also showcased a co-packaged optical engine (COUPE) for silicon photonics, promising an order-of-magnitude reduction in interconnect power. Finally, design-level innovations – from optimized standard cells and memory to AI-assisted EDA tools – are contributing additional efficiency boosts of 5–20% on top of process and packaging improvements. Taken together, these advances reinforce that Moore’s Law is not only alive but augmented by “more-than-Moore” approaches, paving the way for the next era of energy-efficient AI computing.
Major Themes and Technical Innovations
The presentations at IMPACT 2025 centered on several major themes and technical innovations aimed at energy-efficient AI. Below we summarize the primary focus areas that emerged, each of which will be examined in detail in subsequent sections:
Exponential AI Compute Growth vs. Power Limits: AI models and applications are expanding from cloud to edge, driving massive increases in compute requirements (100× or more) and causing power demand to skyrocket. This trend threatens to outpace traditional technology scaling, making efficiency improvements urgent.
Advanced Logic Scaling (FinFET to Nanosheet): TSMC is transitioning its transistor architecture from FinFET to Gate-All-Around nanosheet devices at 2 nm, alongside other node innovations like backside power delivery. These advances continue to provide ~15–30% per-generation power savings and performance gains, which are critical for AI chips.
3D Packaging and Heterogeneous Integration: TSMC’s 3DFabric platform encompasses 2.5D and 3D packaging technologies (CoWoS®, InFO®, SoIC®, etc.) that integrate multiple chips and memory in one package. By shortening communication distances and enabling larger composite dies, these techniques offer significant system-level energy efficiency gains (e.g. 6.7× better power efficiency moving from 2.5D to 3D stacking).
Silicon Photonics for Optical I/O: To overcome electrical I/O power bottlenecks, TSMC is developing co-packaged optical engines (the COUPE architecture) that integrate photonics with silicon. Optical interconnects can reduce per-bit energy by an order of magnitude (5–10× improvement) and cut latency 10–20× versus traditional pluggable optics.
Energy-Efficient Design and EDA: Beyond hardware, TSMC highlighted design-technology co-optimization and AI-assisted design as key to squeezing extra efficiency. This includes new standard cell designs (e.g. optimized flip-flops), dynamic voltage SRAM, compute-in-memory accelerators, and using AI tools for chip layout – collectively yielding additional 5–20% power reductions and productivity gains in chip design.
In the following sections, we delve into each of these areas, drawing on data and slides from the conference to illustrate TSMC’s innovations. The goal is to provide a detailed technical analysis of how TSMC is addressing the power-performance challenge for AI, and what these developments mean for the semiconductor industry going forward.
TPCA: IMPACT 2025｜A Record-Breaking Milestone!
TPCA: This year, IMPACT 2025 reached 5,795 total attendances and 1,122 registrations — both marking our highest record in history! We sincerely thank all our speakers, sponsors, participants, and committee members for your incredible support and contribution.
Together, we have made this 20th-anniversary edition truly remarkable
Thank you for making IMPACT 2025 a record-breaking success!
Your participation and enthusiasm continue to drive innovation, collaboration, and growth across the global electronics community.
IMPACT 2026 will return on October 19–22, 2026 — we can’t wait to see you again for another inspiring year of innovation and ideas!
For Paid Member, SemiVision will discuss topics on
AI Computing Trends and Power Demand
Advanced Logic Innovations: From FinFET to Nanosheet (2 nm and Beyond)
Energy-Efficient Design Techniques (DTCO, Standard Cells, and AI-Assisted EDA)
3D Packaging Technologies and Heterogeneous Integration
SemiVision Tech Insight Report
Looking ahead to 2026, SemiVision will officially launch a new suite of enterprise-level customized services, with core clients focused on Business Development and Market Intelligence teams. These services are designed to help companies navigate the semiconductor industry’s rapid transformation by gaining timely access to decision-grade technology and market intelligence. Rather than simply aggregating information, SemiVision operates through a project-based approach, delivering in-depth, tailored analysis around clients’ priority topics — including technology node evolution, shifting supply-chain roles, competitive landscape restructuring, and emerging commercial opportunities.
SemiVision’s 2026 customized services will center on key areas such as advanced packaging (CoWoS / CoPoS / SoIC / CPO), silicon photonics and Optical I/O, AI and HPC system architecture, bottleneck migration in critical materials and equipment, and the real supply-chain impact of geopolitics and capacity allocation. Through cross-technology and cross-value-chain analysis — integrating process feasibility, production timelines, cost structures, and customer adoption cycles — we support BD and MI teams in identifying which technologies are approaching inflection points, which supplier roles are rising or being displaced, and how complex industry changes can be translated into insights usable for internal decision-making and external strategic communication.
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For readers seeking deeper insight into the structural evolution of the semiconductor industry, SemiVision has long focused on the most critical — yet often oversimplified — core issues. These include advanced and mature node evolution, bottleneck migration in key materials and equipment, competitive–cooperative supply-chain dynamics, and the substantive trade-offs between different technology paths. Beyond organizing public information, we conduct cross-analysis from the perspectives of process feasibility, mass-production barriers, cost structures, customer adoption timing, and long-term competitiveness — helping readers understand why the industry is moving in certain directions and where it may head next. For those requiring more advanced, research-depth industry analysis or customized discussions (such as the technology positioning of specific companies, supply-chain roles, or mid-to-long-term trend assessments), we welcome you to contact us via email for further exchange.：jett@semivisiontw.com、eddyt@semivisiontw.com
SemiVision Tech Insight Report Topics
Advanced Packaging Technology Roadmap and Materials Evolution
Silicon Photonics Platform and Materials Development Trends
Thermal Management Materials for High-Performance Computing and AI Systems
Interposer Architecture and Materials Innovation
Hybrid Bonding Processes and Materials Integration
Through-Glass Via (TGV) Technology and Glass Substrate Development
Key Takeaways from Major Semiconductor Technical Forums
Metalens and Metasurface Optics Materials Evolution
IC Substrate Materials, Process Technology, and Supply Chain Analysis
