Lightmatter Taiwan Tech Day in 20 Minutes: A Photonic Leap into the Future of AI
Original Article By SemiVision Research (Lightmatter, TSMC, ASE, GUC, Synopsys, Cadence, Amkor)
From Chip-Centric to System-Centric: The Computational Paradigm Shift in the AI Era
Lightmatter Taiwan Tech Day 2026 — A Successful Event Bringing Photonics Vision to Taiwan
Lightmatter’s Taiwan Tech Day 2026, held in Hsinchu on January 27/28, 2026, concluded successfully, offering analysts and industry participants an in-depth look at the company’s vision and technology roadmap for next-generation optical interconnects in the AI infrastructure ecosystem. The event featured technical deep dives, strategic discussions on Co-Packaged Optics (CPO), manufacturing scalability, standardization, and system-level integration, helping local audiences better understand Lightmatter’s role and innovations in advancing optical networking for large-scale AI data centers
As artificial intelligence (AI) models grow exponentially in scale, the computing industry is shifting its focus from single-chip performance to overall system architecture. Over the past decade, the number of parameters in AI models has skyrocketed from millions to hundreds of billions and even trillions. For example, large models like GPT-3 and GPT-4 require training across thousands of GPUs in distributed systems. However, with Moore’s Law slowing down, the performance gains of individual chips have become limited.
At the same time, large-scale distributed training introduces massive inter-node communication overhead and synchronization delays, making network bandwidth an increasingly critical bottleneck. NVIDIA CEO Jensen Huang noted that demand for compute power and bandwidth in the latest AI training and inference workloads has surged by a factor of 100 within a single year. This situation forces the industry into a dilemma between “scale up” (enhancing performance per node) and “scale out” (adding more nodes). Simply increasing the number of GPUs leads to network congestion and soaring power consumption, while relying solely on more powerful chips hits the ceiling of semiconductor scaling and thermal limits.
As Lightmatter CEO Nicholas Harris remarked, “The fundamental architecture of the computer is changing. We’ve hit the wall on performance per unit of silicon. The network is becoming the computer, and it has to run on light”. In other words, in the AI era, the boundaries of computation have expanded beyond the chip to encompass entire systems and data centers. Breaking through the bottlenecks of compute and communication bandwidth has become the defining challenge of next-generation computing architecture.
The Data Center Interconnect Bottleneck: The Limits of Copper and SerDes
As AI clusters scale and chip I/O rates continue to rise, traditional electrical interconnects—based on copper wiring—are increasingly revealing limitations in distance and energy efficiency. On high-frequency circuit boards, copper traces suffer from severe signal attenuation and crosstalk, restricting the effective transmission range of high-speed signals to around two meters. Ethernet or InfiniBand cables typically span only one or two server racks.
For instance, NVIDIA’s current NVLink employs copper cables to deliver up to 7.2 Tb/s per GPU (with the Rubin architecture aiming to double this to 14.4 Tb/s). However, these copper links are limited to a maximum range of about 2 meters, meaning even the most powerful GPUs can only be interconnected within a single rack—interconnection cannot be scaled out indefinitely.
Moreover, doubling bandwidth over copper has become increasingly difficult. The Rubin architecture attempts to achieve this by using bidirectional SerDes to double the per-channel data rate, but pushing copper-based communication to 224 Gbps full-duplex per channel is a formidable challenge. Overall, as bandwidth increases, power consumption for electrical interconnects grows non-linearly. According to Broadcom, switch chip bandwidth has increased 80-fold over recent generations, while total system power has grown 22-fold. Power draw from SerDes and optical modules has increased more than three times faster than that of core logic.
High-speed SerDes channels operating at 112 Gbps consume significant power and require complex signal equalization and retimer chips to counteract signal degradation, greatly increasing implementation difficulty. Worse still, large chips are constrained by the number of available package pins and the physical perimeter of the die, limiting the number of I/O channels that can be laid out—a constraint often referred to as the “shoreline bottleneck.” As electrical interconnects approach their physical limits in bandwidth and energy efficiency, continuing to scale compute performance via copper-based links is increasingly unsustainable. This is why co-packaged optics (CPO) and optical I/O are becoming central to the evolution of next-generation data center architectures. Thanks to their inherently low loss, long-range reach, and ultra-high bandwidth, optical communications are widely seen as the inevitable solution to breaking through the compute interconnect bottleneck.
Looking ahead to 2026, SemiVision will launch a new suite of enterprise-level customized services designed for Business Development and Market Intelligence teams. These project-based services deliver decision-grade insights — not just information — helping companies navigate rapid shifts in the semiconductor industry, from technology node evolution and supply-chain restructuring to competitive dynamics and emerging opportunities.
Our focus areas include advanced packaging (CoWoS, CoPoS, SoIC, CPO), silicon photonics and Optical I/O, AI and HPC system architecture, bottleneck migration in key materials and equipment, and the real impact of geopolitics on capacity and supply chains. Through cross-technology and cross-value-chain analysis, we help teams identify inflection-point technologies, rising or displaced supplier roles, and translate complex industry changes into actionable strategy.
Service formats include custom research projects, technology and supply-chain mapping, roadmap comparisons, partnership or investment assessments, and executive-level briefings and training. SemiVision’s role is to bridge technical understanding with market judgment — enabling companies to understand not only what is happening, but why, and how to position accordingly.
For deeper industry analysis or customized discussions, contact:
jett@semivisiontw.com | eddyt@semivisiontw.com
SemiVision Tech Insight Report Topics
From Silicon Photonics to Supply Chain Integration
Introduction — Silicon Photonics as a System-Level Shift
Foundations of Silicon Photonics Platforms
Evolution of CPO Architecture
External Laser Supply and Optical Power Control
Global Silicon Photonics Supply Chain
Taiwan Silicon Photonics Supply Chain
Mid-to-Long-Term Market Structure
Collaboration, Capital, and Ecosystem
SemiVision has long focused on Silicon Photonics and advanced optical interconnect technologies. In response to the data transmission bottlenecks emerging in the AI and HPC era, we have developed highly forward-looking industry perspectives and technical assessments.
We believe that the transition to 400G per lane in photonics is not merely a speed upgrade — it represents a critical inflection point that fundamentally reshapes both system architectures and industry division of labor.
At data rates below 200G per lane, optical interconnects could still be regarded as an extension of high-speed SerDes technologies. However, once systems advance to 400G per lane, traditional electrically dominated design logic becomes fundamentally insufficient. Bandwidth, power consumption, signal integrity (SI), power integrity (PI), package thermal management, and opto-electronic coupling precision simultaneously evolve into tightly coupled system-level challenges.
As a result, silicon photonics is no longer a standalone component or module technology. It is becoming a core platform technology that must be deeply co-designed with advanced process nodes, advanced packaging, and overall system architecture.
400G per Lane: Why This Is a “Qualitative Shift,” Not a “Quantitative Upgrade”
SemiVision identifies 400G per lane as a critical threshold for the following reasons:
Modulation Architectures Are Forced to Evolve
Systems must move beyond traditional NRZ and PAM4 approaches toward higher spectral efficiency. Microring modulators (MRM), Mach–Zehnder modulators (MZM), and DWDM architectures are entering mainstream system design discussions.
DSP and Power Ceilings Are Reached
At 400G per lane, DSP power consumption and latency are no longer merely optimization issues — they directly determine whether a system is viable. This is driving the industry to evaluate DSP-less, Near-DSP, and Optical I/O architectures.
Packaging and Opto-Electronic Integration Become Bottlenecks
Conventional pluggable modules can no longer sustain required power densities and bandwidth levels. Co-Packaged Optics (CPO), Optical Engines, 2D/3D Fiber Array Units (FAU), and chiplet-based optical engines are emerging as the primary battlegrounds for innovation.
SemiVision: Taiwan’s role in the photonics transition is not incremental participation — it is structural indispensability in the global shift toward system-level optical integration.
Taiwan sits at the core of cross-process, cross-packaging, cross-test, and cross-material integration, enabling system-level optical scaling
The Evolving Role of Leading Foundries: From “Manufacturing Service” to “Opto-Electronic Platform Provider”
Another key trend that SemiVision emphasizes is the structural transformation of leading foundries.
Leading foundries are shifting from their traditional role as pure-play wafer manufacturers to becoming high-frequency, high-speed opto-electronic integration platform providers.
This transformation implies:
They are no longer only providing process nodes, but delivering integrated photonic components, electronic circuits, packaging structures, design rules, and production roadmaps.
They are no longer serving single customers in isolation, but building replicable photonic ecosystems.
They are no longer just solving manufacturing challenges, but directly influencing system architecture decisions and the direction of industry standards.
In the 400G per lane era, platform capability itself becomes a fundamental competitive barrier.
The Core of SemiVision’s Unique Perspective
Taken together, SemiVision’s central assessment can be distilled into three key conclusions:
400G per lane marks the true threshold where silicon photonics enters system-level competition.
The decisive factor is no longer individual components, but the depth of integration across process × packaging × opto-electronics × system architecture.
The platformization capabilities of Taiwan’s supply chain and leading foundries represent one of the most difficult-to-replicate strategic assets in the global photonics industry.
Based on the presentations and technical insights shared during Lightmatter Taiwan Tech Day, SemiVision has organized Lightmatter’s position into a structured Industry Ecosystem Overview.
This diagram traces the complete technology and manufacturing flow —
from EDA tools → AI/ASIC → EIC→ PIC → advanced packaging → fiber coupling → laser modules → final testing — providing a clear, system-level perspective on how Lightmatter’s platform connects with the broader semiconductor and photonics value chain.
Rather than viewing photonics as a standalone component, this ecosystem map highlights how electronic-photonic co-design, manufacturing integration, optical assembly, and validation form a continuous stack. The objective is to make the industry architecture, responsibility boundaries, and platform dependencies immediately understandable at a glance, revealing where integration depth and ecosystem coordination create long-term competitive advantage.
