OFC50-Looking Back to Move Forward: Revisiting the 2020 CPO Vision in Light of 2025 Manufacturability Challenges
Original Article by SemiVision Research (Nvidia,Braodcom,Marvell,Intel, AyarLab, Avicena)
Looking Back to Move Forward: Revisiting the 2020 CPO Vision in Light of 2025 Manufacturability Challenges
In 2020, the Optical Internetworking Forum (OIF) hosted a pivotal workshop titled “Co-Packaged Optics: Why, What, and How,” setting the stage for industry-wide discussions around the future of integrated optics in high-performance switching systems. That early dialogue established foundational concepts for CPO architectures, use cases, and ecosystem requirements.
Fast forward to 2025, and the conversation has evolved. At OFC50, the question is no longer “why CPO,” but “how do we make CPO manufacturable?” As discussed in this article, companies such as NVIDIA, Broadcom, and Marvellhave shared practical insights into testability, reliability, and scalable integration strategies, reflecting the industry’s maturity and urgency to overcome real-world deployment barriers.
To build a complete perspective, it is valuable to revisit the earlier technological proposals and visions shared by Intel, Ayar Labs, and Avicena during the formative phase of CPO development. These companies have each proposed unique architectures—ranging from monolithic silicon photonics to near-memory optical interfaces—that continue to shape the manufacturability, packaging, and deployment of optical I/O.
In the next section, we explore and compare the silicon photonics concepts and system-level approaches of Intel, Ayar Labs, and Avicena, as part of a broader technical series. This will be followed by a comprehensive cross-company analysis including NVIDIA, Broadcom, and Marvell, enabling a holistic understanding of how the industry is converging—or diverging—on the path toward scalable Co-Packaged Optics.
First, let’s discuss the four major challenges facing the manufacturability of CPO.
For Paid Members, SemiVision will discuss topics on
Testability: The First Critical Step Toward CPO Mass Production
Broadcom’s Multi-Layer Test Flow
Marvell’s ATE-Based Test Architecture
Key Challenges in CPO Testability
NVIDIA’s Reliability Target
Silicon Photonics Device Reliability
Mitigation Strategy: External Laser Source
Detachable Optical Connectors: A Breakthrough for Yield Enhancement
Key Principles for Scalable Optical-Electrical Integration
Intel’s Perspective on Integration Challenges
Ayar Labs: Three Critical Questions for Mass-Scale Readiness