The 2025 ECTC Semiconductor Summit is about to begin.

2025 ECTC Semiconductor Summit

May 23, 2025

The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the IEEE Electronics Packaging Society (formerly CPMT)

The technical program contains papers covering leading edge developments and technical innovations across the packaging spectrum. Topics include advanced packaging, modeling and simulation, Photonics, interconnections, materials and processing, applied reliability, assembly and manufacturing technology, components and RF, and emerging technologies. Both poster and presentation formats are used. Special papers presented at the ECTC will be awarded the Intel Best Student Paper Award and best and outstanding paper awards.

The Panel, Plenary, Special Sessions, and EPS Seminar provide the conference participants the opportunity to gain the insight and perspective of technical and business leaders.

The ECTC would not be possible without the sponsorship of the IEEE Electronics Packaging Society (formerly CPMT), numerous corporate participants and sponsors, and the time and energy of the more than 200 engineers and scientists on the ECTC Executive and Program Committees.

This year’s ECTC agenda offers deep and highly technical discussions, with a primary focus on Process and Packaging for 3D Integration.

One of the hottest topics is Co-Packaged Optics (CPO), which heavily relies on state-of-the-art hybrid bonding—a key technology in advanced packaging. This is particularly important because TSMC has already applied hybrid bonding in AI chips and optical engines (e.g., for NVIDIA). Looking ahead, if future smartphones begin to adopt hybrid bonding, it would signal a major shift and challenge in mainstream advanced packaging adoption.

In our earlier articles, we discussed that CoWoS-L, despite achieving 9.5x reticle scaling, is reaching new limits, particularly in materials and thermal management. As a result, TSMC is advancing new platforms like SoW-P and SoW-X, with some industry discussions even mentioning CoPoS (Chip-on-Package-on-Substrate) as the next frontier.

This year’s ECTC features several technical sessions and tutorials addressing these challenges. Integration across these technologies will increasingly depend on advanced packaging platforms.

This brings us to the next generation of chip design, where:

System-level co-design becomes essential—integrating logic, memory, optical I/O, and power delivery into one tightly coupled architecture.
Material innovation and thermal management will define manufacturability and scalability.
Hybrid bonding, SoW platforms, and CPO integration will set new industry standards for AI, HPC, and mobile applications.

SemiVision’s Recommendation
As a long-term observer of semiconductor packaging, photonic-electronic integration, AI compute architectures, and next-generation interconnect technologies, SemiVision strongly recommends all readers, researchers, and industry professionals who are passionate about technology innovation to actively participate in the 2025 ECTC.

ECTC is not only the world’s leading forum for advanced packaging and system integration technologies, but also the ideal platform for cross-disciplinary experts and industry leaders to exchange insights and explore future trends. Whether your focus is on process development, design, materials, testing, or application, ECTC offers unparalleled inspiration and collaboration opportunities, driving the next golden decade of technological and industrial advancement.

Welcome to join the 2025 Advanced Packaging and Integration Technology Forum

— a premier gathering where the frontiers of semiconductor packaging, photonics integration, heterogeneous computing, reliability engineering, and thermal-mechanical design converge.

This year’s program reflects the industry’s accelerating push toward system-level performance scaling, addressing the critical demands of AI, high-performance computing, and next-generation connectivity. Across 36 highly specialized oral sessions, experts from across the globe will present cutting-edge developments that reshape the boundaries of chip design, system integration, and manufacturing scalability.

From 3D Integration, Co-Packaged Optics, and Hybrid Bonding to Wafer-to-Wafer Stacking, Large Panel Processing, and RDL Interposer Innovations, the agenda highlights the technologies enabling multi-die architectures and photonic-electronic convergence. As system-in-package (SiP) and system-on-wafer (SoW)approaches mature, this forum offers in-depth exploration into heterogeneous integration, panel-level manufacturing, and bridge/3D stacking solutions that redefine design freedom and performance density.

In parallel, sessions on AI/ML-driven modeling, advanced thermal management, and reliability characterizationtackle the growing challenges of power integrity, signal integrity, and thermo-mechanical stress in high-power, high-density systems. With a spotlight on automotive-grade packaging, additive manufacturing, and wearable technologies, this forum also connects advanced research to real-world applications across automotive, medical, and emerging technology sectors.

Moreover, as Co-Packaged Optics (CPO) transitions from research to deployment, dedicated sessions will detail materials, coupling, and packaging breakthroughs necessary to scale photonic bandwidth to meet the exponential data demands of AI factories and cloud infrastructures.

We invite you to engage deeply with the thought leaders and innovators shaping the semiconductor industry’s next decade — where materials, design, process, and system engineering unite to unlock performance, scalability, and sustainability in the era of data-centric computing.