The Angstrom Era: A Systemic Shift in Semiconductor Innovation from Transistor Scaling to System Co-Design
Original Articles By SemiVision Research (IEEE VLSI , Samsung , TSMC, Nvidia)
The development of semiconductor technology is a topic well worth exploring, as it is deeply interconnected with a wide range of cutting-edge innovations. Key areas such as EUV lithography, High-NA EUV, BSPDN (Back-Side Power Delivery Network), GAA nanosheet transistors, the future transition toward CFETs, and the emerging interest in 2D TMD materials are all frequently discussed at IEEE VLSI symposiums.
In particular, the recent VLSI Forum held in Hsinchu, Taiwan, featured a Panel Presentation that serves as an excellent foundation for in-depth discussion. Given the richness and complexity of the topics presented, we will break down the content and analyze it across several focused themes.
When we talk about the future of semiconductors, most people think of “smaller nodes” or “faster AI chips.” But have you ever considered what it truly means to enter the Ångström Era—where we’re no longer just shrinking transistors, but rewriting the entire architecture of computing itself?
From GAA nanosheets and CFETs, to back-side power delivery (BSPDN), 2D TMD materials, and High-NA EUV lithography, these aren’t just technical buzzwords—they represent a deep transformation that spans chip design, packaging, thermal management, and even how entire data centers are built.
That’s exactly what this year’s IEEE VLSI Forum in Hsinchu, Taiwan, explored in depth. And in this article, we break it all down for you—not just the “what,” but the “why it matters.”
If you’re not just looking for headlines about which foundry is faster, but want to truly understand how companies like TSMC, Intel, Samsung, and ASML are shaping the next decade of technology—this is the deep dive you’ve been waiting for.
We’ll explain the Angstrom Era in a way that’s clear, compelling, and worth your attention.
Path Forward for CMOS Technology in the Angstrom Era — From Microns to Ångströms
This keynote, delivered by Keunhwi Cho, Vice President at Samsung, focuses on the future of CMOS technology as it enters the Angstrom era. It offers not only a retrospective on the evolution of CMOS since the 0.18μm era but also a forward-looking perspective on how AI-driven complexity and packaging challenges are reshaping the scaling paradigm.
From 0.18μm to the Ångström Era: A Historical Perspective
For anyone who has worked in semiconductor manufacturing, CMOS technology is a fundamental and familiar topic—especially for those involved in WAT (Wafer Acceptance Test) analysis, where understanding device physics and solid-state principles is essential. While we won’t dive too deeply into the physics in this article, it’s important to recognize that as we move from microns to nanometers and now to the Angstrom regime, the complexity of scaling continues to grow.
With the shrinking of feature sizes come new challenges, such as short-channel effects, gate control limitations, material constraints, and power-performance trade-offs—all of which demand innovative solutions.
AI Era Design Demands: The Rise of DTCO and STCO
Cho emphasizes that AI chip design has reached a level of complexity that cannot be addressed by traditional scaling alone. The industry is moving beyond classic PPAC (Performance, Power, Area, Cost) metrics, toward Design-Technology Co-Optimization (DTCO) and System-Technology Co-Optimization (STCO).
TSMC, for instance, has adopted the FinFlex concept under its FinFET process at the 5nm node, allowing designers to mix fin configurations for performance or power optimization. Samsung, on the other hand, has led the way in Gate-All-Around (GAA) transistor technology with its MBCFET architecture, debuting at the 3nm node, enhancing channel control and mitigating short-channel effects.
Strategies for the Angstrom Era: GAA and Beyond CMOS
Cho provides an in-depth look at Samsung’s roadmap for GAA technology:
First-generation MBCFETs (Multi-Bridge Channel FET): Employing nanosheet structures to achieve higher drive currents and superior electrostatic control.
Material Innovation: Exploring SiGe and III-V compounds to boost carrier mobility and reduce leakage.
Device-Memory Fusion: Integrating GAA with emerging memories such as MRAM to enable logic-in-memory architectures.
Heterogeneous Integration & Advanced Packaging: Combining GAA with HBM, chiplets, fan-out, and 2.5D/3D stacking to enable modular, high-bandwidth, low-latency SoC platforms.
A New Trajectory: From Process-Driven to System-Driven Innovation
One of the most noteworthy insights in this keynote is the shift from process-driven scaling to system-driven optimization:
In next-generation AI chips, power delivery, thermal management, and signal integrity within the package are just as critical—if not more—than traditional node scaling.
Breakthroughs in the Angstrom era won’t come from lithography alone but will require tight integration across logic, memory, interconnect, and packaging domains.
EDA toolchains must evolve to support multi-level optimization—from device to system—incorporating thermal modeling, power integrity, signal timing, and reliability co-simulation.
Continued Evolution of CMOS Beyond Moore’s Law
While Moore’s Law is slowing down, CMOS is far from obsolete. Cho concludes by stressing that the future of CMOS lies not in further dimension scaling alone, but in co-optimizing materials, architectures, packaging, and system-level performance. Samsung remains committed to advancing GAA-based technologies and strengthening integration across logic, memory, imaging, and packaging platforms.
For Paid Members ,SemiVision will discuss topics on
The Evolution of Microprocessor Technology and Innovation Challenges in the Angstrom Era
Transistor-Driven Innovation: The Foundation of the AI Revolution and the Central Role of Data Centers
Empirical Evidence of AI Advancement: IQ Test Results from Leading LLMs
The Transition from FinFET to GAA: A Pivotal Moment in the Angstrom Era
Data Centers: The Operational Backbone of the AI Era
Thermal Management for AI Chips: Key Challenges and TSMC’s Strategic Response
MOSFET Technology Evolution: Extending Moore’s Law from Planar to GAAFET
HKMG: The Turning Point of Modern CMOS
FinFET to GAAFET: A Generational Shift
Future Outlook: From n-Stack to 2D and 3D Integration
Technology Naming Across Major Foundries: Converging Directions
All Three Foundries Embrace GAAFET: Common Physics, Divergent Optimization
The Critical Relationship Between Process Variation and Chip Performance: Designing from the Worst Case
Why the Slowest Transistor Governs Chip Speed: The Role of Process Variation in Logic Design
Worst-Case Design is the New Gold Standard
EUV and High-NA Lithography: Dual Challenges of Resolution and Defect Control
Resolution Gains and Stochastic Defects
Lithography at the System Level