The 2025 SWTest conference delivered a very clear message to the industry: testing is no longer a supporting role in manufacturing—it has become the central technological hub for advanced packaging, AI/HPC, and optoelectronic integration. As AI GPUs and dedicated accelerators push power consumption to new extremes, chiplets move toward large-scale commercialization, N2/A16 nodes adopt BSPDN, HBM stacks grow deeper, and CPO/OIO enters the early stages of production planning, the entire industry now recognizes a simple truth: without testing, none of the innovations in front-end process or advanced packaging can be realized.
This year, whether from keynote talks by Micron, Marvell, Advantest, Teradyne, MPI and other leading companies, or from technical discussions throughout the forum, one theme was consistent: testing is now essential for high-speed SerDes, KGD validation, multi-stacked memory, system-level reliability, and thermal integrity. As AI/HPC chips increase in package size and push signaling frequency ever higher, test strategies must evolve beyond traditional wafer sort toward a new electrical × optical × thermal tri-domain framework. This shift is gradually turning testing into a critical engineering platform—one that will shape the next decade of semiconductor processes and advanced packaging architectures.
On the other hand, one of the most compelling revelations at this year’s SWTest was the fact that silicon photonics (SiPh), CPO (Co-Packaged Optics), and Optical I/O testing topics finally moved to center stage. From wafer-level photonic test and optical-alignment platforms, to 2D/3D FAU (Fiber Array Unit) coupling accuracy, DWDM multi-wavelength characterization, and BER/eye-performance evaluation for 800G and 1.6T optical engines, the entire photonic-test ecosystem is rapidly converging toward mass-production maturity.
CPO and OIO are among the most critical technologies in today’s AI data-center roadmaps. The deep discussions this year—covering fiber-array tolerances, coupling margins, packaging repeatability, and thermal-variation behavior—clearly show that the industry is now confronting the real barrier of opto-electronic heterogeneous-integration testing. Even more importantly, probers and probe cards are no longer merely electrical interfaces; they are evolving into multi-modal test platforms that simultaneously support electrical probing, optical coupling, and thermal conditioning.
Overall, SWTest 2025 did more than showcase new technologies—it revealed a profound structural shift: testing is redefining the logic of advanced packaging and optoelectronic integration, and over the next 3–5 years, testing will become an unavoidable core battleground for the entire AI semiconductor industry.
In today’s focus, we turn to Metalens, a breakthrough technology that has rapidly drawn intense attention across the semiconductor and photonics sectors. Since TSMC demonstrated the use of Metalens as an optical-coupling element in its COUPE (Compact Universal Photonic Engine) platform, many readers have begun asking:
• What exactly is the role of Metalens? • How is it fundamentally different from traditional µLens or micro-lens arrays? • Why is it emerging as a key interface for silicon photonics (SiPh) in chip-to-fiber and chip-to-chip optical links?
This article aims to answer these questions from a technical perspective. We will break down Metalens working principles, fabrication characteristics, and wavefront-engineering methods, and examine how Metalens can integrate with silicon-photonics platforms—covering grating couplers, edge couplers, meta-surface mode transformers, and more. We will also map out its potential integration pathways in future CPO/OIO architectures.
In other words, after reading this, you should not only understand what a Metalens is—you should clearly see how it opens new engineering design space for next-generation optical packaging and PIC-coupling interfaces.
Driven by the demand for higher bandwidth and lower power consumption in high-performance computing, AI, and data center applications, silicon photonics is rapidly emerging as a key technology for next-generation data transmission and advanced packaging.
The Compact Universal Photonic Engine (COUPE) platform jointly developed by TSMC and NVIDIA is reshaping the landscape of optoelectronic integration. COUPE not only integrates an advanced Co-Packaged Optics (CPO) architecture but also establishes a scalable, production-ready photonic integration framework across optical coupling, packaging, and materials engineering.
Within this ecosystem, the Meta Lens plays an irreplaceable role in optical I/O evolution. Traditional optical couplers rely on 1D Fiber Array Units (FAU), but the growing need for multi-channel, multi-wavelength, and high-density interconnects is driving a transition toward 2D FAU structures. The Meta Lens, with its ultrathin and programmable wavefront control capability, perfectly supports this geometric transition—enhancing fiber-coupling efficiency and beam-shaping performance.
Companies such as Ayar Labs have demonstrated the practicality of integrating Meta Lenses as beam directors and mode-field modulators in optical I/O modules. More importantly, the introduction of emerging materials such as TFLN (Thin-Film Lithium Niobate), BTO (Barium Titanate), and optical polymers provides Meta Lenses with the potential for nonlinear optical effects and hybrid material integration. When these are co-integrated with photonic integrated circuits (PICs) on silicon platforms, Meta Lenses evolve beyond passive focusing—they become active, tunable optical elements capable of adjusting wavelength, polarization, phase, and even performing dynamic control.
Over the past two years, Ayar Labs has clearly accelerated its deployment in the Optical Engine domain, especially as the industry increasingly converges on the positioning of Optical I/O (OIO). According to the latest industry information and public announcements, Ayar Labs has not only entered a deep collaboration with Taiwan’s GUC (Global Unichip Corp.), combining its TeraPHY™ optical-I/O chiplet with GUC’s advanced ASIC design and packaging-integration capabilities, but is also working closely with multiple design teams at AIChip (Alchip Technologies). The goal is to co-develop next-generation optical-electrical interconnect architectures tailored for AI/HPC workloads.
This signals that Ayar Labs now formally regards Taiwan as one of its most critical ecosystems for Optical–Electrical Heterogeneous Integration—not just as a technical partner, but as a true high-volume manufacturing (HVM) supply-chain hub capable of delivering production-scale optical engines.
At the same time, within the broader Optical Interconnection landscape, Ayar Labs’ strategic direction is becoming increasingly differentiated from several rapidly rising photonic-interconnect companies. Celestial AI is pushing its Photonic Fabric; Lightmatter is driving Passage; Lightelligence is focused on photonic-accelerator architectures; and Ranovus is known for low-latency optical links. Each company emphasizes a different “photonics-to-compute” paradigm.
Ayar Labs, however, has a distinctly clear strategy: It focuses on silicon-photonics-based Optical I/O embedded directly inside the package, aiming to replace high-power, EMI-prone, and scaling-limited high-speed SerDes and become the critical communication pathway inside future AI clusters. Put differently:
Celestial AI and Lightmatter are redefining how GPUs communicate with each other.
Ayar Labs is redefining how a chip inputs and outputs data in the first place.
Viewed from a system-level perspective, Ayar Labs now occupies a strategically significant position. Its technology direction aligns directly with a key industry reality: as AI model scales explode, the package boundary has become the new bottleneck. And its intensive collaboration with the Taiwanese ecosystem gives Ayar Labs a credible path toward true HVM readiness.
This is why many recent industry analyses now view Ayar Labs as one of the most important companies to watch as optical engines and optical interconnect rapidly move toward becoming mainstream components of future AI infrastructure.
TSMC’s deepening collaboration with NVIDIA further reinforces the strategic importance of the COUPE platform.
As the COUPE platform advances, it is evident that Meta Lenses hold strategic value in multiple domains—optical packaging, FAU evolution, beam coupling, material integration, and power control. The collaboration between TSMC and NVIDIA underscores a broader paradigm shift: packaging is no longer a purely mechanical process but a multi-dimensional integration of optics, electronics, thermals, materials, and algorithms.
The customizable structural design of Meta Lenses, coupled with their integration into EDA design environments, introduces new challenges for optical parameter synthesis and automated layout generation within the semiconductor design ecosystem. Consequently, from material selection and design workflows to wafer-level fabrication, bonding, packaging, and system integration, Meta Lenses are no longer optional accessories—they are emerging as core modules in next-generation optical packaging.
The industrial value chain surrounding Meta Lenses is expanding rapidly, encompassing mold fabrication, laser direct writing, AI-assisted design synthesis, meta-optical material deposition, and mass-production module packaging. If Taiwan can establish leadership in fabrication process development, EDA integration, and module validation, it will secure a vital position in the global competition for advanced optical platforms.
Optical components play a pivotal role in modern electronic and optoelectronic systems. However, conventional lenses are typically bulky and heavy, posing significant limitations on the miniaturization of optical systems. Meta-lenses, a class of flat optical devices based on metasurfaces, offer a transformative solution by manipulating the phase of incident light at the nanoscale using engineered subwavelength structures on a planar substrate. These ultra-thin, lightweight, and CMOS-compatible optical elements can replicate — and in some cases surpass — the functionalities of traditional curved lenses.
Unlike conventional microlens arrays that rely on geometric curvature for light focusing, meta-lenses enable arbitrary wavefront shaping through spatially varying nanoantenna patterns. This breakthrough opens up novel possibilities for integration into chip-scale systems such as image sensors, AR/VR displays, LiDAR modules, and silicon photonics platforms.
This report provides a comprehensive analysis of meta-lens technology, covering its physical principles and design architectures, performance comparison with traditional microlenses, integration with silicon photonics, fabrication processes and associated challenges, current real-world applications, ongoing research directions, and the key technical hurdles that must be overcome to unlock its full commercial potential.
With the growing demand for optoelectronic integration, we are witnessing for the first time on TSMC’s COUPE platform the use of metalens as a core element for optical coupling—signaling that metasurface technology has officially entered the engineering mainstream of chip packaging and optical interconnects. A metalens is not merely a new type of lens; it is an ultrathin optical interface that can be fabricated directly on a wafer and bonded with optoelectronic components, making it a fundamental building block for CPO, silicon photonics, AR/VR sensing, and 3D light-field systems.
On the COUPE platform, wafer-level optical coupling schemes utilizing metalens structures have already emerged. These leverage subwavelength metasurfaces to achieve high-efficiency, low-tolerance vertical coupling between light-emitting arrays and silicon photonic chips—heralding a future where CPO and Optical I/O systems are defined by ultrathin, wafer-scale, and mass-producible optical designs.
To understand the technology and industry dynamics driving this trend, we will first explore the physical principles and evolution of metalens technology, and then move to its industrial implementation—examining how Hon Hai Research Institute (HHRI) systematically advances metasurface modularization and mass production, while UMC and Metalenz jointly build a large-scale metasurface fabrication line on a 40 nm CMOS platform. Together, these dual axes of system integration and manufacturing illustrate Taiwan’s pivotal role in the emerging metalens/metasurface ecosystem.
Professor Hao-Chung Kuo and Professor Yao-Wei Huang’s team is featured on the cover story of Nano Letters!
The team has successfully developed a monolithically integrated metasurface–PCSEL chip for depth sensing, achieving for the first time the on-chip integration of a metasurface hologram and a photonic crystal surface-emitting laser (PCSEL) to realize a chip-scale structured light projector.
This breakthrough work is published in the world-leading journal Nano Letters and has been selected as the July issue cover and cover story, opening up new possibilities for next-generation biometric identification, extended reality (XR), and consumer electronics depth-sensing technologies.
At this year’s #OFC25 conference and in recent discussions on optical interconnect technologies, optimizing the power efficiency, bandwidth, and transmission range of short-reach interconnects within data centers has become a core topic, driving the emergence of several innovative architectures. Among these, microLED-based optical interconnects have drawn significant attention. MicroLEDs are micron-scale gallium nitride (GaN) light-emitting diodes capable of efficiently emitting photons under electrical current. Unlike traditional VCSELs or external laser sources, microLEDs act as self-emissive microscale light sources, offering a simplified structure, low energy consumption, and full compatibility with CMOS manufacturing platforms—making them ideal for building high-channel-count, massively parallel optical interconnect systems.
The Foxconn Research Institute has provided strategic insights into the silicon photonics industry, underscoring its critical role in meeting the rising demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The institute identifies silicon photonics as a foundational technology for overcoming bandwidth bottlenecks and enhancing energy efficiency within modern data centers. To advance its competitiveness in optical communication and interconnect solutions,
Before delving into the technical foundations of metalenses, it is also crucial to recognize another major shift: Taiwan is no longer merely a base for metal wiring, packaging, and CMOS fabrication, but is becoming a core global hub for transforming metasurface research into commercial products. The most representative example of this transformation is the comprehensive technology roadmap established by HHRI in recent years.
Unlike many research groups still focused on isolated device design, HHRI’s strategy emphasizes system-level integration—spanning metasurface design, wavefront control, active light-source integration, modular packaging, and automated metrology. Through this vertically integrated approach, HHRI has built a metasurface technology stack capable of supporting mass production, marking the first time Taiwan possesses true product-grade metasurface capabilities and forming a complementary linkage with TSMC and UMC on the wafer fabrication side.
In addition to this, the Hon Hai Research Institute recently published a new paper, focusing primarily on the topic of…
It is precisely these synergistic interactions between industry and research that allow us to examine the following topics from a higher vantage point:
Evolution of Metalens Technology and HHRI’s Systematic Development
Since Snellius formulated the law of refraction in 1621, optical design has been fundamentally based on curved-surface lenses. Traditional glass or plastic lenses rely on controlling curvature and optical path differences to focus light — forming the foundation for over four centuries of imaging, photography, and sensing applications.
However, as devices become thinner, chip-scale packaging (CSP) rises, and AI and high-speed optoelectronic systems grow rapidly, these conventional bulky lenses have revealed inherent limitations in volume, weight, and integration.
Entering the 21st century, the maturity of nanofabrication and metamaterial engineering has triggered a fundamental revolution in lens technology. Early 3D metamaterials demonstrated exotic phenomena such as negative refraction and cloaking, but the real turning point came in 2011, when Federico Capasso’s team at Harvard introduced the concept of the metasurface.
This marked a paradigm shift in optical engineering—from 3D refractive structures to 2D subwavelength arrays capable of precisely manipulating phase, amplitude, and polarization.
The metalens, a direct derivative of this concept, achieves optical focusing and wavefront control comparable or even superior to traditional lenses, within only a few hundred nanometers of thickness.
Such characteristics—ultrathin form factor, wafer-level manufacturability, and direct bondability to sensors and photonic chips—make the metalens a foundational enabler of modern optoelectronic integration. Consequently, it has become a core component in Co-Packaged Optics (CPO), optical interconnects, AR/VR, and 3D sensing systems.
In this global wave, the Foxconn Hon Hai Research Institute (HHRI) is taking a markedly different path from academia: instead of remaining at the level of isolated optical designs, it is driving metasurface commercialization through a fully system-level approach. HHRI’s Semiconductor Research Center has designated metasurfaces as an official core research direction, committing long-term resources under a “academia → module → mass production” strategy. Its Meta-PCSEL project with NYCU stands as the best example: by integrating a metasurface directly onto the PCSEL surface, the team reduced the module volume for depth sensing and spatial light-field computation to just 0.025 mm³, lowered power consumption by nearly 30%, and broke through long-standing miniaturization limits of light-field modules. The work not only demonstrates HHRI’s capability in metasurface design, but also establishes its technical depth in active-light-source–integrated metasurface systems. HHRI is simultaneously building results in polarization beam-splitting, wavefront control, and other domains, indicating that its roadmap has already moved beyond passive components into active-source architectures.
HonHai’s greatest advantage is not a single optical breakthrough, but its vast manufacturing and packaging infrastructure, which enables metasurfaces to be inserted directly into mass-production-ready processes. From WLP and CSP to heterogeneous integration, optical module bonding, passive alignment, and automated testing, Foxconn possesses the full production chain required to meet metasurface demands for large-area uniformity, bonding precision, and module-level packaging. This makes HHRI one of the very few teams globally capable of taking optical design all the way to product-grade module integration—particularly suited for AR/VR light-field engines, 3D sensing, LiDAR, and the emerging generations of optical I/O and CPO interconnects. Metalenses can be applied directly to beam engineering at the FAU, VCSEL, and PD interfaces in these systems, offering high degrees of design freedom and extremely compact form factors. Overall, HHRI’s direction has already moved beyond the boundaries of traditional research institutions, gradually establishing a “mass-producible metasurface module platform”—a strategic position that will shape Taiwan’s role in the next era of optical semiconductors.
UMC × Metalenz: The Strategic Logic Behind Building the World’s First Large-Scale Metasurface Production Line on a 40 nm CMOS Platform
Unlike HHRI’s system-level approach, UMC (United Microelectronics Corporation) is pioneering a globally rare, forward-looking strategy from the wafer-level manufacturing side. In 2025, Metalenz announced that it would adopt UMC’s 40 nm CMOS platform to fabricate its meta-optics layer and perform wafer-on-wafer (W2W) bonding with image sensors using a 300 mm production line. This collaboration positions Taiwan as the world’s first semiconductor base capable of true large-scale metasurface mass production.
The critical factors for metalenses are not transistor density but subwavelength structural fidelity—feature linewidths, sidewall profiles, film-stack stability, and large-area pattern uniformity. Metalens meta-atoms (nanopillars or nanofins) typically fall within 40–100 nm for visible wavelengths and 80–200 nm for NIR. Research has further confirmed that visible-light metalenses can achieve minimum feature sizes below 50 nm. UMC’s 40 nm platform offers sufficient lithography resolution, alignment accuracy, film quality, and etch control to meet these requirements—without resorting to expensive, over-spec EUV nodes.
The key insight is this: metasurfaces require large-area, highly regular, repetitive nanoscale arrays, a process profile that naturally aligns with the maturity, stability, and high yield of the 40 nm CMOS generation. Since entering mass production in 2008, the platform has accumulated extensive process know-how, equipment uniformity, and low defect density—precisely the foundational conditions for scaling meta-optics manufacturing.
Meanwhile, W2W bonding demands stringent control over planarity, overlay, and material-layer stability. Paradoxically, a mature node like 40 nm achieves higher bonding yields and lower process risk than advanced nodes. After all, metalenses are optical components rather than logic chips; their value lies in structural precision × large-area scalability × low cost × high consistency, not transistor-level linewidth scaling. Importantly, a CMOS “node” name does not represent the actual minimum printable feature size—40 nm platforms can reliably fabricate sub-50 nm meta-atoms after lithography and etch tuning, making them ideal for visible and NIR metalens production.
The UMC–Metalenz partnership thus marks the birth of the world’s first metasurface production line with true CMOS-grade manufacturing scalability. With a mature process platform, 300 mm capacity, W2W integration, and sustainable expansion potential, UMC has become an indispensable manufacturing anchor within the global meta-optics ecosystem.
From an industry perspective, Taiwan—through the dual pillars of UMC and HHRI—has formed a complete chain spanning design, fabrication, packaging, and module-level integration. This positions Taiwan strategically across next-generation applications including CPO, optical I/O, AR/VR, 3D sensing, and wafer-level optics.
For Paid Member, SemiVision will discuss topics on
Technological Evolution and Industrial Applications of Metalenses: A Comparative Analysis of Metalens vs. Microlens and COUPE Integration
Microlens (MLA) vs. Metalens: Operating Principles and Performance Differences
Process Comparison: From Glass Shaping to Nanopillar Arrays
Fabrication Methods for Metalenses
TSMC COUPE Platform and Metalens Integration
Role of Microlenses in COUPE
Role of Microlenses in COUPE (uLens Arrays)
Challenges of Nanopillar Structures
Metalenz and UMC Advance Polar ID Metalens Face-Recognition Module Into Mass Production, Opening a New Era of Low-Power, High-Security Biometric Sensing
Integration of Meta-Lenses with Silicon Photonics Platforms
Meta-Lens in Co-Packaged Optics (CPO)
Intra-Chip and Interconnect Meta-Lens Applications
Meta-Lenses in Optical I/O and Vertical Coupling
Fabrication Processes and Manufacturing Challenges of Meta-Lenses
IMEC: Advancing Optical Interfaces for Silicon Photonics and AR
MIT: Leading Innovations in Tunable and Ultra-Wide-Angle Meta-Lenses
Meta (Facebook): Toward Flat Optics for AR/VR Headsets
1. Metalens Interface Design on Silicon Photonic Chips
2. Integration Opportunities: Metalens in TSMC’s COUPE / CPO Platforms
3. High-Aspect-Ratio Nanopillars and the Process Limits of Dense Metasurface Patterns
What Taiwanese Companies Must Strengthen to Enter Metalens + Silicon Photonics Manufacturing
Matching Metalens Processes to Silicon Photonics Flows
From Research Validation to Mass Production: Becoming Part of the Wafer-Level Optics Manufacturing Flow
Ecosystem and Collaboration Models
Metalens Commercialization Requires a Clear, Collaborative Value Chain
Future Opportunities: Differentiation Advantages Under Massive Market Potential Finally, let’s address the question many people have been asking: What exactly is Himax’s strategy in metalens?
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