Where Systems Meet Devices: VLSI & DRC 2025 — The Complete Semiconductor Experience

Original Articles by SemiVision Research (2025 VLSI , 2025 DRC Tech Conference)

As the Generative AI Wave Sweeps the Globe, the Semiconductor Industry Faces a Critical Inflection Point

The global semiconductor industry is undergoing a profound transformation amidst the sweeping rise of generative AI. From silicon wafers to system-level packaging, major semiconductor conferences worldwide are now converging their focus on the design and manufacturing challenges brought by AI chips. At the heart of this revolutionary shift are NVIDIA and TSMC, who together have been pivotal in accelerating the development of AI infrastructure and next-generation compute chip architectures.

As AI chip compute density and power requirements continue to climb, design complexity is growing exponentially. Take for example TSMC’s upcoming 2nm process and the future A16 node—both embody a radical shift. In the absence of High-NA EUV lithography, TSMC has adopted a System Power Rail (SPR) architecture that relocates the Frontside Power Rail (FS) to the backside of the chip (BS Power Rail), introducing unprecedented challenges in physical design and power integrity.

This shift renders traditional DTCO (Design-Technology Co-Optimization) insufficient. Instead, it demands a dual-level synergy between DTCO and STCO (System-Technology Co-Optimization) to strike a delicate balance between performance, power, and reliability at advanced nodes.

The introduction of BSPDN (Backside Power Delivery Network) not only reshapes power delivery but also brings major thermal management challenges. At the IEEE IITC 2025 conference, Professor Kuan-Neng Chen from National Yang Ming Chiao Tung University presented a landmark paper titled:

“Thermal Performance Analysis of BSPDN and FSPDN From Chip to Package Level”

The study conducts a comprehensive chip-to-package-level thermal analysis comparing backside and frontside power delivery networks. It underscores the need for rethinking packaging, thermal materials, and layout strategies when implementing BSPDN in advanced chips.

In parallel, leading IEEE technical conferences such as ECTC 2025 also showcased numerous TSMC papers exploring CoWoS®, SoW®, silicon photonics, and heterogeneous integration—highlighting their depth in high-bandwidth and high-efficiency advanced packaging technologies.

IITC 2025 further served as a platform for forward-looking research from both global industry leaders and academic institutions, addressing integration bottlenecks in next-generation process technologies. In addition to his BSPDN work, Professor Chen also presented:

“Advanced CMP Optimization for Enhanced Cu/Polymer Hybrid Bonding in 3D IC”

This research dives into how chemical mechanical planarization (CMP) techniques can be optimized to improve the quality and stability of Cu/polymer hybrid bonding—a critical challenge in 3D IC integration. The findings carry significant implications for improving interface reliability in advanced packaging.

As we move into June, the semiconductor industry enters a pivotal season of technical forums and international conferences. Of particular interest is the upcoming VLSI Symposium 2025 – Cultivating the Future of Innovation. Widely regarded as the flagship event in logic and circuit design, the symposium brings together global technology leaders and research pioneers to discuss next-generation strategies for chip design, device architecture, and system integration in the AI era.

We will continue to monitor and report on key insights and breakthroughs presented at VLSI Symposium 2025, bringing our readers front-line perspectives from the cutting edge of semiconductor technology.

#VLSI2025 Highlight on Advanced Packaging
“High-Density Wafer Level Connectivity Using Frontside Hybrid Bonding at 250nm Pitch & Backside Through-Dielectric Vias at 120nm Pitch After Extreme Wafer Thinning” – imec (Paper T6-1)
imec demonstrates high-density wafer level connection using face-to-face hybrid bonding at 250nm pitch and backside through-dielectric vias at 120nm pitch. Access from the wafer backside is demonstrated through extreme wafer thinning beyond shallow trench isolation floor.

#VLSI2025 Highlight paper on Advanced CMOS Technology
“Intel 18A Platform Technology Featuring RibbonFET (GAA) and Power Via for Advanced High-Performance Computing” – Intel (Paper T1-1)
An advanced Intel 18A technology featuring RibbonFET and Power Via provides over 30% density scaling and a full node of performance improvement compared to Intel 3. Intel 18A offers high-performance (HP) and high-density (HD) libraries with full-featured technology design capabilities and enhanced design ease of use.

#VLSI2025 Highlight on Digital Circuits, Hardware Security & Signal Integrity
“A 77fJ/bit 8 Gbps Low-Latency Self-Timed Die-to-Die Link for 2.5D and 3D Interconnect in 3nm (Paper C7-3)
NVIDIA researchers present a self-timed die-to-die serial link for 2.5D and 3D stacked die interconnects using a standard adaptive digital clock and voltage supply. The link achieved 8Gbps/pin bandwidth with a 1 cycle latency, energy efficiency of 77fJ/b, and 44 Tbps/mm2 at 07V in a 3nm process.

#VLSI2025 Highlight on Image Sensor Technology
““A Back-illuminated 10um-pitch SPAD Depth Sensor with 42.5% PDE at 940nm using Optimized Doping Design” – Sony Semiconductor Solutions (Paper T1-2)
The research was conducted using a 10μm-pitch single-photon avalanche diode (SPAD) depth sensor with a back-illuminated (BI) structure on a 300mm CMOS platform. To enhance photon detection efficiency (PDE), the multiplication region design was optimized to increase the triggering probability for the Geiger mode, and an optimized doping design was introduced to enable more efficient charge collection. As the results, the world's highest PDE of 42.5% at 940nm was achieved.

#VLSI2025 Highlight on Memory Technologies, Devices, Circuits, and Architectures
“A 3nm FinFET 563kbit 35.5Mbit/mm2 Dual-Rail SRAM with 3.89pJ/access High Energy Efficient and 27.5uW/Mbit 1-cycle Latency Low-Leakage Mode," TSMC (Paper C4-1)
Authors at TSMC demonstrate a high-density (HD) 6T SRAM for mobile applications using the eXtended Dual Rail XDR architecture and two key techniques. The Delaying- Write-WL (DeWL) technique resolves the problem of contention between the cell and the write-driver (WDRV), and the 1-cycle latency low-leakage mode (1-CLM) reduces power by turning off BL pre-chargers during no operation (NOP) periods. A 3-nm FinFET test chip achieves a 17% reduction in active energy and a 10% decrease in standby leakage.

#VLSI2025 Highlight on Wireline & Optical Transceivers, Optical Interconnects Processors
“A 128Gb/s 0.67pJ/b PAM-4 Transmitter in 18A with RibbonFET and PowerVia," Intel (Paper C12-2)
Researchers at Intel present a fully integrated 128-Gb/s DAC-based transmitter (TX) designed for long-reach wireline applications in 18A CMOS process with RibbonFET, PowerVia and a backside power delivery network. The backside power layer is also used for inductors and clock distributions. The TX achieves the best energy efficiency of 0.67 pJ/bit (0.75 pJ/bit with the PLL) and the smallest area reported while meeting key electrical compliance specifications for PAM-4 standards

As the 2025 VLSI Symposium draws to a close, the global spotlight in the semiconductor community now shifts to another premier event—the 2025 Device Research Conference (DRC). Following in the footsteps of VLSI, DRC brings together leading experts from academia and industry to delve into the latest advances in electronic and photonic devices. These two back-to-back conferences together capture the full spectrum of semiconductor innovation—from system architecture to device physics—highlighting the industry’s continued momentum and groundbreaking research in the era of AI.

Organizational Structure and Committee

The DRC organizing committee is composed of leading experts from both academia and industry, ensuring the technical program remains forward-looking and of the highest quality. The Technical Program Chair for DRC 2025 is Dr. Tania Roy from Duke University. The event also features invited speakers and contributors from major semiconductor companies such as IBM, Intel, TSMC, Micron, and ASE, who will share their latest work on advanced device engineering and system integration.

Focus Areas of DRC 2025

Reflecting the latest frontiers in device research, DRC 2025 will cover the following thematic areas:

• Heterogeneous Integration and 3D ICs

• Neuromorphic Computing and Emerging Memory Technologies

• Wide Bandgap and 2D Material Devices

• Optoelectronic and Quantum Devices

• Device Simulation and Modeling

Plenary Speakers of DRC 2025

This year’s plenary speakers include a diverse lineup of thought leaders from academia and industry:

• Prof. Eli Yablonovitch (University of California, Berkeley): Discussing circuit designs that solve optimization problems using physical inequalities.

• Dr. Charles Lu (Chairman of Etron Technology and President of AI-on-Chip Taiwan Alliance): Addressing the co-evolution of the semiconductor and AI industries, and the challenges of symbiotic growth.

• Prof. Suman Datta (Georgia Institute of Technology): Offering insights into the future trajectories of microelectronics.

In addition to these plenaries, leaders from IBM, Intel, TSMC, Micron, and ASE will present their latest breakthroughs in advanced device architecture and integration technologies.

For eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 83rd anniversary of the DRC—the longest-running device research meeting in the world. The high-caliber technical sessions are highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

The 2025 Conference will feature:

• An informative, timely short course in rapidly developing fields

• Oral and poster presentations on electronic/photonic device experiments and simulations

• Plenary and invited presentations given by worldwide leaders

• Evening rump sessions

• Strong student participation and Student Paper Awards

• Focus sessions on devices for Heterogeneous Integration

DRC will be held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 25-27. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences.

DRC 2025 Short Courses Highlight Emerging Trends in BEOL Integration and Device Modeling

As part of its ongoing mission to foster deep technical exchange and frontier research, the 2025 Device Research Conference (DRC) presents two specialized Short Courses aimed at addressing some of the most critical challenges and breakthroughs in device engineering and modeling. These half-day sessions bring together distinguished experts from leading global institutions to deliver foundational and forward-looking insights to researchers, engineers, and students working at the cutting edge of semiconductor technology.

Short Course 1: Heterogeneous Integration at the BEOL — Challenges from Device to System Level

Organized by Biwajit Ray and Kai Ni, this short course dives into the rapidly evolving landscape of Back-End-of-Line (BEOL) heterogeneous integration, an area that is becoming increasingly essential for scaling beyond the limitations of conventional transistor design. As Moore’s Law slows, BEOL integration offers promising paths to enhance density, functionality, and energy efficiency in next-generation computing systems.

Featured Speakers:

• Prof. Shimeng Yu

  School of Electrical and Computer Engineering, Georgia Institute of Technology

  Title: Applications of Amorphous Oxide Semiconductor Transistors at BEOL

  Prof. Yu explores how amorphous oxide semiconductor (AOS) transistors are redefining possibilities in BEOL architectures. These devices offer high mobility, low-temperature process compatibility, and scalability that make them ideal for monolithic 3D integration.

• Prof. Gong Xiao

  Professor, Department of Electrical and Computer Engineering, National University of Singapore (NUS)

  Title: Unlocking Ultra-High Density and Energy Efficiency in 3D Integrated Circuits with BEOL-Oxide Semiconductor Technology

  Prof. Xiao addresses the material and design innovations necessary to realize ultra-high-density 3D ICs. His talk focuses on how oxide semiconductors can be utilized to push energy efficiency to new levels within the BEOL layer.

• Prof. Madhavan Swaminathan

  Professor of Electrical Engineering, Penn State University

  Title: The Future of Heterogeneous Integration: Challenges and Opportunities

  A leading voice in advanced packaging and system design, Prof. Swaminathan will offer a systems-level perspective on heterogeneous integration, discussing the interdependencies between materials, thermal management, electrical signaling, and architecture co-design.

Short Course 2: Fundamentals of Device Modeling

Organized by Prof. Avik Ghosh and Prof. Shaloo Rakheja, this course offers a deep dive into the foundational and computational aspects of electronic and quantum device modeling. As devices shrink to nanometer and atomic dimensions, accurate modeling from first principles is critical for predicting behavior and optimizing performance.

Featured Speakers:

• Prof. Shaloo Rakheja

  Associate Professor, Electrical and Computer Engineering, University of Illinois at Urbana-Champaign (UIUC)

  Title: From Atoms to Assemblies of III-Nitride Technology for High-Frequency Communication and Sensing Applications

  Prof. Rakheja discusses how atomistic modeling enables the design of III-nitride based devices tailored for RF and sensing, highlighting multiscale simulation methods that bridge materials science and electronic transport.

• Prof. Branislav Nikolic

  Professor of Physics, University of Delaware

  Title: Computational Time-Dependent Quantum Transport for Spintronics and Magnonics

  A pioneer in quantum transport theory, Prof. Nikolic will present state-of-the-art numerical techniques for simulating spin-based devices and dynamic processes in magnetic systems, key to future non-volatile memory and logic.

• Prof. Avik Ghosh

  Professor, Electrical and Computer Engineering, University of Virginia

  Title: First Principles Numerical Modeling of Optoelectronic and Photonic Devices

  Prof. Ghosh will illustrate how ab-initio and tight-binding approaches are applied to simulate photonic and optoelectronic device behavior, with relevance to emerging silicon photonics, lasers, and modulators.

These two short courses reflect DRC’s dedication to bridging fundamentals with forward-looking research directions. Whether exploring new device topologies at the BEOL or developing the modeling tools to understand quantum phenomena, the courses promise to deliver insight and inspiration to engineers and researchers shaping the next decade of microelectronics innovation

For more information about the 83rd Device Research Conference (DRC 2025), including the full agenda, registration details, travel and accommodation tips, and sponsorship opportunities, please visit the official conference website:

https://2025.deviceresearchconference.org/

The website includes:

• Program Overview – A complete schedule of short courses, plenary talks, technical sessions, poster presentations, industry panels, and the traditional rump session.

• Registration Information – Details on registration fees, early bird discounts, student participation, and invitation letter requests.

• Venue and Lodging – Recommended accommodations, campus maps (Duke University, NC), and safety tips regarding booking scams.

• Sponsorship & Exhibition – Opportunities for companies to connect with the global semiconductor community through booth packages and branding exposure.

DRC 2025 will be held from June 22–25, 2025, at Duke University in Durham, North Carolina. Attendees will have the opportunity to engage with leaders from companies like IBM, Intel, TSMC, Micron, and ASE, and explore cutting-edge topics in heterogeneous integration, 2D materials, AI chips, and advanced packaging.