Intel Showcases Groundbreaking Innovations at IEDM 2024
Advancing Heterogeneous Integration, GAA Transistors, and Ruthenium Interconnects for the Next Era of Semiconductor Technology
At IEDM 2024, Intel plans to deliver two invited talks and present seven research papers. During a pre-event briefing for the press, Sanjay Natarajan, Senior Vice President and General Manager of Intel's Technology Research Group, previewed some of the innovations Intel plans to showcase.
Heterogeneous Integration (HI)
Intel highlighted advancements in HI, a technique enabling the combination of various chiplets tailored for specific functions into a single product. This trend allows for greater flexibility in CPU designs, such as Lunar Lake, and is pivotal for next-generation computing.
Traditionally, HI chiplets were produced using two methods:
Wafer-to-Wafer (W2W): Bonding two dies of the same size and technology at the wafer level, which is cost-effective.
Chip-to-Wafer (C2W): Placing chiplets onto a separate wafer, which is more expensive and time-consuming.
Intel introduced a breakthrough by utilizing inorganic infrared lasers to debond over 15,000 chiplets (each measuring 1 mm²) from a single wafer within minutes. They emphasized the importance of modularity in future chiplet stacking technologies and announced developments in next-generation EMIB.
EMIB (Embedded Multi-die Interconnect Bridge)
The original concept of silicon bridge invention likely did not originate from Intel. TSMC also had related invention concepts in the early days. However, Intel refined the silicon bridge and applied it to 2.5D packaging, achieving not only excellent computational performance and low power consumption but also cost savings. Intel has effectively carved out its own path in advanced packaging technology using EMIB, avoiding direct competition with TSMC's CoWoS technology.
Compared to other multi-die integration packaging technologies, Intel emphasizes the advantages of its EMIB technology:
EMIB is compact, resulting in shorter signal transmission paths between dies.
It does not require through-silicon vias (TSVs) or interposers, simplifying the manufacturing process.
It enhances computational performance.
Additionally, improvements in GAA performance were demonstrated by covering molybdenum disulfide (MoS₂) electrodes with hafnium oxide (HfO₂), achieving subthreshold swing improvements (75 mV/d or better). This advancement reinforces the possibility of sustaining Moore's Law with GAA technology, a topic expected to be explored in one of Intel's invited talks.
Additionally, improvements in GAA performance were demonstrated by covering molybdenum disulfide (MoS₂) electrodes with hafnium oxide (HfO₂), achieving subthreshold swing improvements (75 mV/d or better). This advancement reinforces the possibility of sustaining Moore's Law with GAA technology, a topic expected to be explored in one of Intel's invited talks.
Transistor Innovations
Intel also shared updates on its RibbonFET, a Gate-All-Around (GAA) transistor design, used in Intel 20A, 18A, and 14A nodes. Intel has prototyped highly efficient transistors with a gate length of 6 nm and a fin thickness of 1.7 nm.
RibbonFET
RibbonFET is Intel's solution to this problem at 5 nm or below. RibbonFET, called nanosheets by other groups, utilizes a stack of semiconductor sheets to form the channel. Whereas the gate in a FinFET covers the channel region on three sides, the nanosheets are surrounded by the gate, classifying the device as a gate-all-around (GAA) device. This architecture leads to improved electrostatic control of the transistor, faster transistor switching speeds, and acceptable driving currents in a smaller footprint.
The semiconductor industry agrees that for nodes below 3nm, transistors must adopt the GAA (Gate All Around) FET architecture to overcome the electrical characteristic challenges posed by further size scaling. Currently, TSMC still utilizes the FinFET architecture for its 3nm process, although GAA is under development. Samsung, on the other hand, refers to its GAA technology as MBCFET and plans to introduce it for mass production in 2022.
In fact, GAA FET was first invented in 1986. In 2006, South Korea's KAIST published a paper on 3nm GAA FETs. However, creating samples in a laboratory and achieving mass production are entirely different levels of complexity.
Intel 20A plans to adopt RibbonFET transistors, a GAA architecture, at the 20-angstrom node in 2024. Intel has also showcased wafer photos and electron microscope images of the development, proving it is not just theoretical but actively progressing.
Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and Rapidus.
Interconnect Technology
Intel plans to present research on ruthenium (Ru)-based interconnect layers, which could replace traditional materials like copper and aluminum in future processes. Ru interconnects have been highlighted as promising for the 2 nm node by international research groups such as imec. However, Intel clarified that this technology is aimed at future process nodes and will not be used in near-term manufacturing.
Conclusion
Intel’s preview offered a glimpse into its innovations, with more detailed announcements expected at IEDM 2024. This year’s highlights include advancements in heterogeneous integration, transistor technology, and interconnect materials. Intel also revealed that the Technology Research Group, formerly known as "Component Research," was renamed to better reflect its modern focus. These changes underscore Intel's commitment to driving technological innovation forward.
About IEEE IEDM
With a history stretching back more than 65 years, the IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. IEDM is truly an international conference, with strong representation from speakers from around the globe.
As always, great work on presented materials. Thank you.
"plans to introduce it for mass production in 2022."
?