Intel’s Secret Weapon: The 18A Process and Its Bold Comeback
Original Article by SemiVision Research
Technical Positioning and Benchmarking
Intel’s 18A process is technically considered to be on par with TSMC’s A16 (which includes GAA (Nanosheet) architecture and SPR (Super Power Rail)).
Intel 18A introduces a key technology known as PowerVia, which is a new backside power delivery technology. This innovation plays a significant role in enhancing the performance and efficiency of Intel’s advanced semiconductor processes. Below is a detailed introduction to PowerVia:
What is PowerVia?
PowerVia is Intel’s proprietary backside power delivery system designed for its 18A process node. Traditionally, power delivery to a chip’s transistors occurs via the front side of the chip, where power and ground connections are routed through metal layers on the surface of the chip. However, this method can have limitations, such as increased power consumption, signal interference, and challenges with scaling as transistors become smaller.
PowerVia changes this by moving the power delivery to the backside of the chip, which improves overall efficiency and reduces power loss. The system connects to the power grid via a specialized backside power plane, allowing for more efficient distribution of power and better thermal management.
Key Features of PowerVia:
1. Improved Power Efficiency:
By placing the power delivery network on the backside, PowerVia allows for a more direct and less obstructed path to power the transistors. This reduces the resistance and power loss typically seen in traditional power delivery methods, especially at smaller nodes like 18A.
2. Enhanced Performance:
With better power delivery comes the potential for higher performance. PowerVia helps to reduce voltage drop (IR drop) across the chip, which can improve the overall speed and stability of the processor. This makes it particularly valuable for high-performance workloads and AI-driven applications.
3. Reduced Signal Interference:
Traditional power delivery systems can lead to signal noise, as the power and signal lines share the same space on the chip. PowerVia eliminates this issue by separating power delivery from signal routing, which can result in cleaner, more reliable signal integrity, especially at higher speeds.
4. Better Thermal Management:
The backside power delivery system also helps with thermal management, as the power grid can be spread out more evenly across the chip. This helps in heat dissipation, which is crucial as transistor density increases.
5. Compatibility with Advanced Technologies:
PowerVia works synergistically with other advanced technologies like Intel’s RibbonFET (a new transistor architecture introduced in the 18A process). RibbonFET and PowerVia together enable significant performance improvements at the atomic level of the transistors, offering an optimal solution for next-generation processors.
Advantages of PowerVia in Intel 18A Process:
• Enables Higher Power Density: With backside power delivery, Intel can pack more transistors into the same area without compromising on power efficiency, which is essential for high-performance chips in AI, data centers, and mobile devices.
• Improves Chip Scaling: As Intel continues to scale down to smaller nodes like 18A, traditional power delivery methods face limitations due to the increasing complexity and density of transistors. PowerVia helps overcome these scaling challenges, making it easier to achieve higher transistor counts without power or thermal limitations.
• Supports High-Performance Computing: PowerVia is particularly important for AI and machine learning applications that require high processing power and energy efficiency. It helps ensure that Intel’s chips can support the most demanding workloads with lower energy consumption.
Comparison with TSMC’s Approach:
Intel’s PowerVia technology positions the company ahead of competitors like TSMC in terms of backside power delivery. While TSMC is expected to incorporate a similar technology in its later process nodes (likely with its A16 processes), Intel has been a pioneer in implementing PowerVia earlier in the 18A process, giving it a performance and efficiency edge.
Cadence Joins Intel Foundry Accelerator Design Services Alliance
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Cadence's inclusion in this ecosystem accelerates innovation by offering tech designers the resources they need to bring groundbreaking projects to life. From systems on chip (SoCs) to advanced IP for artificial intelligence (AI) and high-performance computing (HPC) applications, the alliance helps Intel Foundry customers remain at the forefront of innovation.
Cadence provides design tools, ASIC development expertise, and support for Intel’s advanced technologies like Intel 18A with RibbonFET transistors and PowerVia power delivery.
TSMC will adopt the SPR (Super Power Rail) approach for the A16 process, but for processes below A16, it will begin a dual-track approach, including A14, A12, and A10. Some of these nodes will be paired with SPR, while others will not. We will provide an explanation for paid members.
Future Impact of PowerVia:
PowerVia is expected to play a significant role in Intel’s roadmap for future processes beyond 18A. It will help Intel meet the power, performance, and area (PPA) targets for its next-generation processors, including those for AI, HPC, and consumer devices. As Intel scales down to even smaller nodes, PowerVia will be key in maintaining the balance between power efficiency and performance, which is essential for the advancement of semiconductor technology.
In summary, PowerVia is a groundbreaking technology for Intel, offering a more efficient and effective way to deliver power to transistors on the 18A process. It helps Intel address critical challenges in power efficiency, thermal management, and performance scaling, positioning Intel as a leader in advanced semiconductor design.
SemiVision Research will provide an in-depth explanation of TSMC’s design for SPR (Super Power Rail) in the future, including an explanation of the SPR process flow, PDK (Process Design Kit), package, SPR supply chain, and more.
For paid members, SemiVision Research will discuss topics on
Yield Status
Production Capacity Progress
High NA EUV Adoption in 18A Process
Customers and Applications
Future Outlook and Challenges
Summary
SemiVision Research has organized the future ASIC development plans for Intel and Broadcom and will provide explanations on these topics.
