TSMC's Advanced Packaging: Pioneering the Future of Semiconductor Integration

Exploring the Innovations of CoWoS, InFO, and 3DFabric® Technologies Driving HPC and AI applications

3DFabric Alliance

The 3DFabric Alliance is the first of its kind in the semiconductor industry and aims to achieve the following goals with the collaborative efforts of our OIP (Open Innovation Platform) ecosystem partners.

Source: TSMC

TSMC's 3DFabric offers our customers the ultimate flexibility in product design, brings packaging technologies to the forefront for innovation, and are critical to a product's performance, function and cost.

Source: TSMC

3DFabric's Complete System Integration Portfolio

• 2D Packaging - InFO

• 2.5D Packaging - CoWoS®

• 3D Packaging - SoIC, InFO-3D

This article primarily introduces the three types of CoWoS.

• CoWoS-S

• CoWoS-R

• CoWoS-L

Source: TSMC

TSMC’s CoWoS-S (chip last) platform, highlighting its capabilities for high-performance computing applications.

Key Features:

1. High Performance and Integration Density:

   • The CoWoS-S platform offers industry-leading performance and the highest integration density, making it ideal for demanding computing workloads.

2. Wafer-Level System Integration:

   • The platform supports a wide range of interposer sizes, accommodates multiple HBM cubes, and allows for flexible package configurations.

3. Larger Interposer Sizes:

   • CoWoS-S enables interposer integration larger than 3X reticle size (approximately 2,550 mm²), which supports the integration of advanced System-on-Chip (SoC) designs with more than four HBM cubes.

Source: TSMC

TSMC ‘s CoWoS-R (chip last), a member of the CoWoS® advanced packaging family, and its features for high-performance computing and heterogeneous integration.

Key Features:

1. InFO Technology and RDL Interposer:

   • CoWoS-R leverages InFO (Integrated Fan-Out) technology and uses an RDL (Redistribution Layer) interposer to serve as an interconnect between chiplets.

   • It is especially suited for applications involving HBM and heterogeneous SoC integration.

2. Flexible RDL Interposer Design:

   • The RDL interposer is composed of polymer and copper traces, offering mechanical flexibility.

   • This flexibility enhances the C4 bump joint integrity (connections between the chip and substrate), ensuring reliability in high-performance applications.

3. Scalability for Complex Packages:

   • The flexible RDL design allows for scalability, enabling the creation of larger and more complex packages to meet demanding functional requirements.

Source: TSMC

CoWoS-L, a chip-last packaging solution within TSMC's CoWoS® platform, designed for high-performance computing and advanced heterogeneous integration.

Key Features:

1. CoWoS-L Overview:

   • CoWoS-L combines silicon interposer and fan-out technologies to enable flexible integration of chiplets and components.

   • It uses an interposer with LSI (Local Silicon Interconnect) for efficient die-to-die interconnects and RDL (Redistribution Layer) for power and signal delivery.

2. High Integration Capacity:

   • CoWoS-L starts with 1.5X reticle size interposers that support configurations such as 1 SoC + 4 HBM cubes. (5.5X reticle size in 2026)

   • The platform is scalable to larger sizes, accommodating more complex designs and additional chips for high-performance workloads.

3. Advanced Packaging Design:

   • The diagram illustrates multiple chips (Chip 1 and Chip 2) integrated on an interposer with LSI connections, which ensures seamless communication and power delivery between components.

   • The RDL layers enhance flexibility, allowing custom configurations for demanding applications like AI, machine learning, and data centers.

Source: TSMC

3DFabric® is a versatile and scalable solution for next-generation semiconductor designs, seamlessly integrating multiple advanced packaging technologies to push the limits of compute density, performance, and system size. This innovation is pivotal for industries like AI, data centers, and advanced computing.

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