MediaTek: Enabling Generative AI: Innovations and Challenges in Semiconductor Design Technologies
Original Articles By SemiVision Research ( IEEE VLSI , MTK , Nvidia)
Unlocking a New Engine for Future AI Computing Power: MediaTek’s Transformation Trajectory and Full-Stack Deployment
As the wave of generative AI sweeps across the globe, the demand it brings is no longer just about stacking GPUs in the cloud. Rather, it signifies a structural reshaping of the computing architecture—from a traditional "SoC mindset" to one centered on "system integration and heterogeneous collaboration." Once known primarily for its focus on mobile communications and mid-tier SoCs, MediaTek is now undergoing a platform-level transformation across chip design, heterogeneous packaging, photonic interconnects, and edge AI in the era of AI innovation.
At the 2025 IEEE VLSI Symposium, a pivotal panel presentation led by MediaTek clearly outlined the company’s comprehensive strategy across four key axes: AI ASIC design, intelligent edge, automotive platforms, and CPO (co-packaged optics) interconnects. This presentation was more than just a roadmap of how a company expands beyond a single application domain to become a leader in custom AI chips—it also reflects the broader redefinition of East Asia’s IC design ecosystem within the global restructuring of AI computing infrastructure.
From SoC to ASIC: A Technological Strategy for Reconstructing Core Value
Over the past decade, MediaTek has leveraged its smartphone chip business to expand into the global market, successfully challenging traditional incumbents. However, in the AI era—marked by the growing demand for heterogeneous computing and massive-scale deployments—MediaTek has initiated a structural transformation: evolving its core capabilities from mobile SoCs toward customizable AI ASIC platforms.
Through a comprehensive RTL-in to GDSII-in design service flow, MediaTek has successfully transformed into an ASIC company equipped with four key integrated capabilities: high-efficiency design, flexible process support, diverse packaging, and high-speed interconnects.
During its presentation at VLSI 2025, MediaTek revealed—for the first time—its full-scale strategy for custom AI chip development. By leveraging its in-house development of advanced SerDes (112G / 224G), SoC design optimized for STCO/DTCO, leading-edge process technologies (such as 3nm and TSMC N2), and advanced packaging approaches (like CPO and CPC), MediaTek is enhancing its PPA (Performance, Power, Area) advantages. These capabilities not only serve its mobile platform customers but also directly support hyperscalers in developing next-generation AI superchips.
MediaTek stated that its AI ASIC designs have already secured multiple design wins, with plans to contribute substantial revenue starting in 2026, targeting over USD $1 billion in annual revenue. Some of these customers are rumored to include U.S. tech giants such as Google (potentially related to TPU projects), while others are believed to be connected to NVIDIA’s NVLink integration efforts—a clear indication that MediaTek is carving out a new strategic position in the cloud AI domain.
Co-Developing the Future of AI Infrastructure Modules with NVIDIA
Notably, MediaTek’s collaboration with NVIDIA has expanded from in-vehicle cockpit platforms to data center modules. Together, the two companies have co-developed the GB10 AI module, featuring over 1,000 TOPS of AI computing power. Designed to support training for large language models with up to 200 billion parameters, the GB10 serves as a prototype foundation for personal-scale AI supercomputers. The launch of this module marks a significant shift in MediaTek’s role—from a terminal SoC supplier to a comprehensive AI solutions partner.
The GB10 integrates a MediaTek-led xPU AI processor, utilizing multi-die modular packaging, and supports MCP (Memory-Compute Proximity) as well as A2A (Agent-to-Agent) architectures. This enables the module to handle not only AI inference but also lightweight training and multi-agent collaborative computing, positioning it as a critical compute node in the emerging Smart Edge ecosystem.
According to public information, MediaTek is also working with NVIDIA to advance the NVLink Fusion architecture. Fusion represents a GPU-centric chip design philosophy, allowing third-party ASICs or SoCs to connect to NVIDIA GPUs and CPUs via standardized high-speed interfaces. As one of the initial partners in NVLink Fusion, MediaTek is not merely an IP integrator but also a co-architect of cross-die computing frameworks. This strategic alliance lays the groundwork for MediaTek to further participate in next-generation projects—such as LLM training clusters and potential AI H100 successors.
Strategic Deployment of Edge Intelligence and AI Agents
Another key focus area for MediaTek is the widespread adoption of edge AI platforms, using its mobile device expertise as a bridge. Between 2024 and 2025, MediaTek plans to roll out a new generation of SoCs across Chromebooks, IoT devices, smart tablets, TVs, and wearables. These SoCs are built on advanced 3nm process technology and feature NPUs capable of delivering over 50 TOPS. They support multimodal tasks such as voice assistants, image generation, and behavioral reasoning, while enabling low-power consumption, localized learning, and on-device LLM inference—paving the way for a new paradigm of on-device AI agents.
MediaTek sees AI agents as a key application frontier. The company is streamlining the deployment of GenAI models with optimized toolchains, while also improving memory efficiency and cybersecurity protections. This strategy targets increasingly fragmented yet latency-sensitive AI scenarios, such as smart home voice assistants, industrial IoT devices, and medical diagnostic tools. MediaTek is positioning its edge SoCs as “agent-ready” platforms, laying the foundation for the next wave of AI-driven use cases.
AI Smartphones and Smart Cockpits: Full-Scale High-End Integration
In its traditional stronghold of smartphones, MediaTek is further strengthening its generative AI capabilities. The newly launched D9400+ flagship SoC supports inference for major LLMs like Llama and Gemma, powered by an 8th-gen APU for energy-efficient model acceleration. It also features advanced co-processors for voice, image, and visual AI tasks. This SoC is scheduled for commercial release in Q2 2025, with an upgraded version planned for 2H25, already backed by multiple global OEMs—marking MediaTek’s solid foothold in the flagship AI smartphone segment.
The automotive sector represents another promising frontier. MediaTek has unveiled the DX1, the world’s first 3nm cockpit chip, offering integrated NPU, RTX-class GPU performance, and AI capabilities for multi-display and multi-camera setups. The platform has already gained traction with major Chinese automakers and is expanding into European and Indian markets. MediaTek is now positioned as a strong contender in the automotive AI space, following Qualcomm and NVIDIA. With compatibility to the NVIDIA Drive ecosystem, MediaTek opens up new opportunities ranging from mid- to high-end cockpit integration to future ADAS collaboration.
Breaking Through the Value Chain: MediaTek's Deployment in CPO and Photonic Interconnect Ecosystem
As high-performance computing (HPC) and AI training workloads continue to push data center I/O to its limits, MediaTek is not only advancing in transistor technology and packaging, but also actively venturing into next-generation photonic interconnects. A critical piece in this strategy is its collaboration with Ranovus.
Ranovus is one of the few companies worldwide capable of mass-producing Co-Packaged Optics (CPO) platforms. Its Odin™ photonic engine combines a highly integrated silicon photonics platform with hot-swappable modularity, supporting single-mode 800G to 1.6T communication standards. With both integrated and external laser options, Odin™ meets various modular deployment needs. At OFC 2024, MediaTek and Ranovus jointly demonstrated an 8×800G electrical-optical integrated solution, combining MediaTek’s 112G SerDes with Ranovus’ Odin™ engine, successfully validating their CPO packaging technology.
This partnership clearly reflects MediaTek’s ambition to build a unified electro-optical integration platform. As one of the few IC design companies globally with in-house capabilities in SerDes, packaging, SoC, and IP licensing, MediaTek is constructing a high-speed interconnect value chain from AI ASIC → SerDes → CPO integration. This not only fills Ranovus’ gap in customer adoption and large-scale deployment but also empowers MediaTek with end-to-end solution capabilities and stronger bargaining power in building hyperscale AI training clusters.
For Paid Members, SemiVision will publish an in-depth analysis of MediaTek and NVIDIA’s strategic transformation in the AI era, with a special focus on how MediaTek is evolving from a SoC vendor into a full-stack AI ASIC design powerhouse. We will also cover MediaTek’s latest developments in Edge AI, voice assistant devices, and automotive platforms (including smart cockpits and ADAS), as well as its critical collaborations with NVIDIA on NVLink Fusion, GB10, and CPO solutions.
SemiVision will discuss topics on
MediaTek's Edge AI Development and Collaboration with NVIDIA: Observations and Future Directions
1. MediaTek’s Edge AI Development: History and Current Status
2. MediaTek and NVIDIA’s Collaboration in the ASIC Domain
3. NVLink Fusion: GPU-Centric Architecture and MediaTek’s Role
MediaTek’s Role in NVLink Fusion: Technical Integration and Strategic Implications
MTK’s Business and Ecosystem Synergy
4. MediaTek’s Development Strategy in Automotive Chips and Smart Cockpit Platforms
Dimensity Auto Smart Cockpit Platform Highlights
ADAS, Autonomous Driving, and Cockpit Integration Strategy
Seamless Integration of Dimensity Auto with NVIDIA ADAS Systems
Collaboration with NVIDIA in Automotive AI
Joint Development and Future Roadmap