2025 VLSI – Paths Forward for CMOS Technology in the Ångström Era: Scaling Limits, 2D TMD Integration, Interconnect Challenges, and System-Level Co-Optimization
Original Article by SemiVision Research (Samsung , TSMC, Nvidia , Lab 91)
From Microns to Ångströms: Why Interconnection Defines the Future of CMOS
In his keynote speech at the IEEE VLSI Symposium, Keunhwi Cho, Vice President at Samsung Electronics, presented “Path Forward for CMOS Technology in the Angstrom Era — From Microns to Ångströms.” While the talk reflects on the historical evolution of CMOS scaling from the 0.18μm era, its core insight lies in how interconnection—not just transistors—will shape the trajectory of system performance as we enter the Angstrom regime.
Beyond Scaling: A Shift from Process-Centric to System-Driven Innovation
As feature sizes shrink from microns to nanometers to Ångströms, the limitations of traditional transistor scaling have become apparent: short-channel effects, gate control challenges, material limitations, and power-performance tradeoffs. These challenges no longer reside purely at the device level—they have migrated to the interconnect infrastructure, which now defines the boundaries of performance, efficiency, and system scalability.
Interconnection at the Heart of DTCO and STCO
As Cho emphasized, the complexity of AI-era chip design demands more than classic PPAC (Performance, Power, Area, Cost) metrics. The industry is rapidly embracing Design-Technology Co-Optimization (DTCO) and System-Technology Co-Optimization (STCO), where interconnects play a central role.
TSMC’s FinFlex technology and Samsung’s GAA (MBCFET) architecture exemplify innovations at the transistor level, but without dense, low-loss, high-bandwidth interconnects, their system-level benefits cannot be fully realized.
Enabling the Angstrom Era: Beyond Transistors—Interconnect is the Platform
Cho outlined Samsung’s future roadmap for integrating GAA technologies with advanced packaging and system integration, where interconnects are the enabler:
Backside Power Delivery (BSPDN) + Hybrid Bonding: Enhances power efficiency, reduces IR drop, and improves thermal paths while tightening interconnect density and reliability.
GAA + MRAM + HBM: Creates low-latency, logic-in-memory SoC platforms—enabled by high-density vertical and lateral interconnects.
Chiplet Architectures with 2.5D/3D Packaging: Requires ultra-high-density interconnects using CoWoS or FO-PLP platforms to ensure seamless modular integration.
High-Frequency Data Interconnects: As AI workloads demand explosive bandwidth, NRZ/PAM4 electrical interconnects and optical I/O technologies become indispensable.
CMOS Is Not Dead—Interconnect Drives Its Continued Evolution
While Moore’s Law may be slowing, CMOS is far from obsolete. As Cho concluded, the future of CMOS will not be defined by lithographic scaling alone, but by co-optimization across materials, device architectures, interconnects, and system packaging.
In the era of AI and HPC, interconnect is no longer a passive link—it is a first-class design element that governs power, performance, and scalability. From BSPDN to hybrid bonding, from GAA to co-packaged optics, the interconnect stack is the foundation upon which future semiconductor systems will be built
SemiVision’s latest article delves into the domain of Interconnect Technologies, asserting that 3D stacking must rely on interconnection via hybrid bonding for its success.
At the IEEE IITC forum, one of the most respected conferences dedicated to advanced packaging technologies, a wealth of papers in 2025 extensively explore interconnection innovations. Proceedings clearly demonstrate the centrality of interconnect research to the future of chip integration .
Notably, Professor Kuan‑Neng Chen from NYCU has authored multiple papers featuring back-side power delivery networks (BSPDN) analyses under thermal constraints, alongside studies on hybrid bonding techniques . His work underscores the critical role of coupling BSPDN with hybrid bonding to address heat dissipation and integration density issues.
Industry leaders such as Applied Materials (AMAT) and Besi also presented key contributions on hybrid bonding within wafer-to-wafer and die-to-wafer processes, demonstrating improvements in overlay accuracy and bonding yield .
SK hynix featured papers highlighting integration strategies to support future HBM‑4 and HBM‑5 memory stacks, tackling interconnect designs optimized for high‑bandwidth memory architectures.
Samsung Electronics explored scaling challenges in advanced node CFET and memory logic, including discussions of bonding-enabled connectivity for co-packaged optics and CFET interconnect structures.
Moreover, UNIST (Ulsan National Institute of Science and Technology) contributed several technical presentations at IITC 2025, reflecting South Korea’s strong presence in semiconductor interconnect research .
Why IITC 2025 Is Essential for Interconnect Technology
Comprehensive coverage of BEOL/MOL/chiplet bonding: IITC consistently focuses on advanced metallization, integration flows, and unit processes across interconnect domains .
Hybrid bonding as the enabler of future integration: As reviewed by Prof. Chen, hybrid bonding—metal-metal and dielectric-dielectric interfaces—is crucial for ultra-dense chiplet integration and improved thermal and performance characteristics .
BSPDN and hybrid bonding interplay: Research combining BSPDN network engineering with hybrid bonding improves both electrical power distribution and thermal management in 2nm‑node and beyond architectures.
Strong industry-academic collaboration: The conference brings together key voices from academia and industry giants such as IMEC, IBM, Samsung, SK hynix, AMAT, Besi, and UNIST to address system-level interconnect challenges .
IITC 2025 serves as a critical technical forum where expert speakers and industry researchers converge to address how 3D stacking depends on reliable and scalable interconnects. Through discussions on BSPDN, hybrid bonding, thermal dissipation, and high‑density memory integration, this conference anchors itself as an authoritative platform for the interconnect-driven future of semiconductor innovation.
As semiconductor manufacturing advances into the Ångström era, traditional silicon channels are reaching their physical scaling limits. Two-dimensional transition metal dichalcogenides (2D TMDs), such as MoS₂ and WSe₂, have emerged as promising candidates to extend CMOS scaling. With atomically thin bodies, excellent electrostatic control, and steep subthreshold slopes, TMDs are ideal for ultra-short gate lengths and are well-suited for next-generation device architectures like GAA and CFET.
While n-type TMD devices have already demonstrated impressive on-state performance, the development of high-performance p-type counterparts still faces challenges—particularly in contact resistance and threshold voltage tuning. Issues such as Schottky barriers at metal–TMD interfaces, material non-uniformities, and device variability continue to hinder large-scale adoption. Institutions like Intel and IMEC are working to address these hurdles by developing fully integrated process flows, including low-temperature deposition, nanoribbon stacking, gate dielectric engineering, doping, and contact optimization. Initial applications are expected in non-critical domains such as power management or I/O, serving as a transitional phase before integration into high-performance logic.
If these barriers can be overcome, 2D TMDs hold the potential to become key enablers for logic devices beyond the 1.4nm node. More than just a materials breakthrough, their adoption would signal a shift toward system-level co-optimization across device, process, and packaging domains—marking a new milestone in the post-Moore era of semiconductor innovation.
Lab 91 is working on developing Transition Metal Dichalcogenide (TMD) based devices in various application domains, including optoelectronic/photonics. An example implementation maybe a monolithically integrated on-chip laser (replacing InP and associated complex packaging steps) or electro-optic SERDES, taking advantage of MoS2’s tunable bandgap (in monolayer form, it has a direct bandgap of 1.6 to 1.8 eV, which compares favorably to InP which has s direct bandgap of 1.3 eV)
For Paid Members ,SemiVision will discuss topics on
Next-Generation Interconnects in Logic Process Technology: From Dual-Damascene to 2D Material Integration
New Materials: Beyond Copper and Barriers
Structural Innovations: Air-Gaps and High Aspect Ratio Lines
Long-Term Strategy: 2D/1D Materials and Semi-Damascene
Co-Evolution of Process, Material, and Structure
Backside Power Delivery: A Key Technology to Solve Metal Congestion and Power Efficiency Challenges
The Era of Heterogeneous Integration: Chiplet Architectures and the Trillion-Transistor Leap
From N5 to A10: Process Shrink and Packaging Innovation in Tandem
Advanced Packaging and 3D IC: TSV and Hybrid Bonding Usher in a New Era of Heterogeneous Integration
Hybrid Bonding: A Breakthrough for Interconnect Density
Evolution of Packaging Platforms: From RDL to Interposer
3D IC: From Packaging Stacking to a Core Enabler of Performance and Power Efficiency
3D IC: Architectural Breakthrough Through Logic-Memory Partitioning